dsn = prj.create_design_module(lib_name, cell_name)
print('design parameters:\n%s' % pprint.pformat(params))
dsn.design_specs(**params)
# implement the design
print('implementing design with library %s' % impl_lib)
dsn.implement_design(impl_lib, top_cell_name=cell_name, erase=True)
# generate the layout
layout_params = dsn.get_layout_params(**layout_params)
pprint.pprint(layout_params)
cProfile.runctx(
'temp_db.new_template(params=layout_params, temp_cls=NPassGateWClk, debug=False)',
globals(),
locals(),
filename='passgate_stats.data')
temp = temp_db.new_template(params=layout_params,
temp_cls=NPassGateWClk,
debug=False)
temp_db.batch_layout(prj, [temp], [cell_name], debug=True)
#temp.write_summary_file('%s.yaml' % cell_name, impl_lib, cell_name)
temp.write_summary_file('adc_sampler_ec.yaml', impl_lib, cell_name)
'''
#lvs
print('running lvs')
lvs_passed, lvs_log = prj.run_lvs(impl_lib, cell_name)
if not lvs_passed:
raise Exception('oops lvs died. See LVS log file %s' % lvs_log)
print('lvs passed')
'''
# create design module and run design method.
print('designing module')
dsn = prj.create_design_module(lib_name, cell_name)
print('design parameters:\n%s' % pprint.pformat(params))
dsn.design_specs(**params)
# implement the design
print('implementing design with library %s' % impl_lib)
dsn.implement_design(impl_lib, top_cell_name=cell_name, erase=True)
# generate the layout
layout_params = dsn.get_layout_params(**layout_params)
pprint.pprint(layout_params)
cProfile.runctx(
'temp_db.new_template(params=layout_params, temp_cls=NPassGateWClk, debug=False)',
globals(),
locals(),
filename='passgate_stats.data')
temp = temp_db.new_template(params=layout_params,
temp_cls=NPassGateWClk,
debug=False)
temp_db.batch_layout(prj, [temp], [cell_name], debug=True, flatten=False)
temp.write_summary_file('%s.yaml' % cell_name, impl_lib, cell_name)
#lvs
print('running lvs')
lvs_passed, lvs_log = prj.run_lvs(impl_lib, cell_name)
if not lvs_passed:
raise Exception('oops lvs died. See LVS log file %s' % lvs_log)
print('lvs passed')