def _setUpTest(self):
# Ensure vector element size is set to 32 bits and vector register group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 0,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, 'VECREG', exclude='0')
self._mElemVals1 = self._initializeVectorRegister('v%d' %
self._mRegIndex1)
self._mElemVals2 = self._initializeVectorRegister('v%d' %
self._mRegIndex2)
def _setUpTest(self):
# Allowing fractional VLMULs and any valid VSEW values
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 10,
"0x2": 10,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 10,
"0x6": 10,
"0x7": 10,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, "VECREG", exclude="0")
self._initializeVectorRegister("v%d" % self._mRegIndex1)
self._initializeVectorRegister("v%d" % self._mRegIndex2)
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 10,
"0x1": 10,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
# Ensure vector register group size is no more than 4, as larger values
# are not legal for widening and narrowing instructions
vlmul_choice_weights = {
"0x0": 10,
"0x1": 10,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 10,
"0x6": 10,
"0x7": 10,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# TODO(Noah): Remove the restriction on SEW when a mechanism to skip instructions with
# illegal vector layouts is implemented. For now, ensure vector element width is set to no
# more than 32 bits.
choice_weights = {
'0x0': 10,
'0x1': 10,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
choice_weights)
# Ensure vector register group size is no more than 4, as larger values are not legal for
# widening and narrowing instructions
vlmul_choice_weights = {
'0x0': 10,
'0x1': 10,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 10,
'0x6': 10,
'0x7': 10
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
# Ensure vector element size is set to 16 bits and vector register
# group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 10,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices(
"vtype.VSEW", vsew_choice_weights
)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices(
"vtype.VLMUL", vlmul_choice_weights
)
choices_mod.commitSet()
self._initializeVectorRegisters()
def _setUpTest(self):
# Allowing fractional VLMULs and any valid VSEW values
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 10,
'0x2': 10,
'0x3': 10,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 10,
'0x6': 10,
'0x7': 10
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, 'VECREG', exclude='0')
self._initializeVectorRegister('v%d' % self._mRegIndex1)
self._initializeVectorRegister('v%d' % self._mRegIndex2)
def _setUpTest(self):
# Ensure vector element size is set to 16 bits and vector register group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 10,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
self._initializeVectorRegisters()
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
# enable exception delegation for some portion of the generated tests.
delegation_enables = ChoicesModifier(gen_thread)
weightDict = {"0x0": 0, "0x1": 50}
delegation_enables.modifyRegisterFieldValueChoices(
"medeleg.Instruction page fault", weightDict)
delegation_enables.commitSet()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# TODO(Noah): Remove the restriction on SEW when a mechanism to skip instructions with
# illegal vector layouts is implemented. For now, SEW = 64 ensures all applicable
# instructions can be legally generated.
choice_weights = {'0x0': 0, '0x1': 0, '0x2': 0, '0x3': 10, '0x4': 0, '0x5': 0, '0x6': 0, '0x7': 0}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW', choice_weights)
choices_mod.commitSet()
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
delegation_enables = ChoicesModifier(gen_thread)
weightDict = { "0x0":0, "0x1":50 }
delegation_enables.modifyRegisterFieldValueChoices( 'medeleg.Instruction address misaligned', weightDict )
delegation_enables.commitSet()
(paging_opt, valid) = gen_thread.getOption("PagingDisabled")
if valid and paging_opt == 1:
gen_thread.initializeRegister(name='satp', value=0, field='MODE')
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
delegation_enables = ChoicesModifier(gen_thread)
weightDict = {"0x0": 0, "0x1": 50}
delegation_enables.modifyRegisterFieldValueChoices(
'medeleg.Breakpoint', weightDict)
delegation_enables.modifyRegisterFieldValueChoices(
'medeleg.Environment call from U-mode', weightDict)
delegation_enables.commitSet()
(paging_opt, valid) = gen_thread.getOption("PagingDisabled")
if valid and paging_opt == 1:
gen_thread.initializeRegister(name='satp', value=0, field='MODE')
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 0,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# Ensure element size is at least 32 because smaller sizes are not legal
choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 10,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
# 64-bit elements are illegal in 32-bit mode for vector atomic instructions
if self.getGlobalState("AppRegisterWidth") == 32:
choice_weights["0x3"] = 0
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
# Ensure vector element size is set to 32 bits and vector register
# group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, "VECREG", exclude="0")
self._mElemVals1 = self._initializeVectorRegister("v%d" %
self._mRegIndex1)
self._mElemVals2 = self._initializeVectorRegister("v%d" %
self._mRegIndex2)