def circuit(self):
super().circuit()
R = Resistor()
stiff_voltage = Divider(type='resistive')(V=self.V,
V_out=self.V_split +
0.6 @ u_V,
Load=self.I_b)
stiff_voltage.input += self.v_ref
stiff_voltage.gnd += self.gnd
stiff_voltage.v_ref += self.v_ref
splitter = Bipolar(type='npn', common='emitter',
follow='collector')(collector=R(self.R_out),
emitter=R(self.R_out))
split = stiff_voltage & self & splitter
self.output = Net('OutputInverse')
self.output_n += splitter.collector
self.output += splitter.emitter
R_in = R.parallel_sum(
R,
[self.R_out * 2, stiff_voltage.R_in, stiff_voltage.R_out]) @ u_Ohm
self.C_in = (1 / (2 * pi * self.f_3db * R_in)) @ u_F
signal = Net('VoltageShiftAcInput')
ac_coupling = signal & Capacitor()(self.C_in) & self.input
self.input = signal
def circuit(self):
super().circuit()
self.C_in = (1 / (2 * pi * self.f_3db * self.R_in)) @ u_F
self.C_out = (1 / ((2 * pi * self.f_3db) *
(self.R_e + self.R_load))) @ u_F
signal = self.input
self.input = Net('ACGainInput')
ac_input = self.input & Capacitor()(self.C_in) & signal
output = self.output
self.output = Net('ACGainOutput')
ac_output = output & Capacitor()(self.C_out) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('GndCapacitorOutput')
C_gnd = signal & self.output & Capacitor()(self.C_gnd) & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('GndResistorOutput')
R_gnd = signal & self.output & Resistor()(self.R_gnd) & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('RLCOutput')
L_parallel = signal & Inductor()(self.L_parallel) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('SeriesResistorOutput')
R_series = signal & Resistor()(self.R_series) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('RLCOutput')
C_parallel = signal & Capacitor()(self.C_parallel) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('SeriesInductorOutput')
L_series = signal & Inductor()(self.L_series) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('VrefCapacitorOutput')
C_v_ref = self.v_ref & Capacitor()(self.C_vref) & self.output & signal
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('GndInductorOutput')
L_gnd = signal & self.output & Inductor()(self.L_gnd) & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('SeriesCapacitorOutput')
C_series = signal & Capacitor()(self.C_series) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('FilterLowpassOutput')
low_pass = signal & Resistor()(self.R_low) & self.output & Capacitor()(
self.C_pass) & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('FilterHighpassOutput')
high_pass = signal & Capacitor()(
self.C_block) & self.output & Resistor()(self.R_shunt) & self.gnd
def circuit(self):
super().circuit()
R = Resistor()
D = Diode(type='generic')
signal = self.input
self.input = Net('CompensationInput')
ref_point = Net('CompensationDropVref')
"""
Only a small positive upswing from the input is required to bring it to conduction. Because the input is capacitively coupled,
it is pure AC. Its swings are additively superimposed on top of the bias voltage that exists on the other side of the capacitor.
The 5V source is just from somewhere in the rest of the circuit. There is nothing special about it.
"""
ac_coupling = Filter(highpass='******')(V=self.V, f_3dB_high=self.f_3dB, Load=self.R_stiff)
self.input & ac_coupling & signal
"""
The 𝑅1, 𝑅3 and 𝐷1 circuit basically creates a 0.6V bias on the other side of the capacitor, so that a positive swing
in the signal does not have to overcome a 0.6V hurdle. 𝐷1 and 𝑅3 form a shunt voltage regulator.
"""
voltage_regulator = ref_point & R(self.R_stiff) & self.v_ref
"""
The purpose of R1 is to act as a flexible linkage to separate the reference 0.6 voltage, which is quite stiff,
from the point where the signal is injected, which must on the contrary be free to swing about 0.6V.
R1 also protects the diode from the input current swings. If we replace R1 by a wire, it won't work because
the signal will try to move the voltage at the top of D1, whose cathode is pinned to ground.
The input's positive swings will dump current through D1, abusing it. That creates a poor input impedance,
resulting in an inability to generate the right voltage on or under D2.
On the other hand, if R1 is made large, the compensation diminishes, because the reference
voltage is able to exert less control over the bias.
"""
compensator = ac_coupling.gnd & ref_point & D() & self.gnd
"""
A negative swing of 0.1V turns to 0.5V. But this cannot create a -0.1V output at the bottom of D2; that is nonsense
because it is outside of our supply range. 0.5V is not enough to forward bias D2, and so the output is at 0V,
pulled to ground by R2, which has almost no current flowing across it to create any voltage.
"""
after_pull = self.output & R(self.R_stiff * 10) & self.gnd
def circuit(self):
super().circuit()
shifter = RLC(series=['C'], gnd=['R'])(
C_series=self.C_shift_in,
R_gnd=self.R_shift_out,
)
shifter.input += self.output_n
shifter.gnd += self.output
self.output = Net('ShiftedSignal')
self.output += shifter.output
self.output_n = None
def circuit(self):
super().circuit()
output = Net('FilterBandpassOutput')
# Sink resistor
R_band = Resistor()(self.R_band)
# Inductor tanker
L_tank = Inductor()(self.L_tank)
C_tank = Capacitor()(self.C_tank)
# Filter Network
self & R_band & output & (L_tank | C_tank) & self.gnd
self.output = output
def assign_pins_to_block(block):
pins = pins_definition(block.pins)
for pin in pins.keys():
pin_description = [pins[pin]] if isinstance(pins[pin],
bool) else pins[pin]
device_name = ''.join([
name for name in block.name.split('.')
if name[0] == name[0].upper()
])
net_name = device_name + ''.join(
[word.capitalize() for word in pin.split('_')])
related_nets = [pin]
# pin = True, str -- Net(pin_name | str)
# pin = Int -- Bus(pin_name, Int)
original_net = getattr(block, pin, None)
if type(pin_description) in [list, tuple]:
for pin_data in pin_description:
if isinstance(pin_data, str):
net_name = device_name + pin_data
if isinstance(pin_data, list):
related_nets += pin_data
else:
if isinstance(pin_description, int):
original_net = Bus(pin, pin_description)
else:
net_name = device_name + pin_description
if not original_net:
original_net = Net(net_name)
original_net.fixed_name = True
for net in related_nets:
setattr(block, net, original_net)
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('VrefInductorOutput')
L_v_ref = self.v_ref & Inductor()(self.L_vref) & self.output & signal
def circuit(self):
self.input = self.output = self.input or Net('PulseGeneratorInput')
def ref_input(self):
ref = Net('Reference')
line = self.input & Resistor()(self.R_e) & ref
return ref
def circuit(self):
self.input_n = Net('ACGainSplitN')
super().circuit()
def willMount(self, V_ref=15 @ u_V):
if not self.gnd:
self.gnd = Net()
self.load_block = Virtual()(input=self.output, output=self.output_n)
self.load(self.V_ref)