def wrcsr(reg, val): bus.write_2(io, 0x12, reg & 0xffff) bus.write_2(io, 0x10, val & 0xffff)
def wrbcr(reg, val): bus.write_2(io, 0x12, reg & 0xffff) bus.write_2(io, 0x16, val & 0xffff)
def rdcsr(reg): bus.write_2(io, 0x12, reg & 0xffff) return bus.read_2(io, 0x10)
pcicfg = bus.map(dev, 'pcicfg') logging.debug('pcicfg=%s (%s)' % (pcicfg, dev)) vendor = bus.read_2(pcicfg, 0) device = bus.read_2(pcicfg, 2) if vendor != 0x1022 or device != 0x2000: logging.error('Not an AMD PCnet-PCI (vendor=%x, device=%x)' % (vendor, device)) sys.exit(1) command = bus.read_2(pcicfg, 4) if not (command & 1): logging.info('enabling I/O port decoding') command |= 1 bus.write_2(pcicfg, 4, command) if not (command & 4): logging.info('enabling bus mastering') command |= 4 bus.write_2(pcicfg, 4, command) bus.unmap(pcicfg) io = bus.map(dev, '10.io') logging.debug('io=%s (%s)' % (io, dev)) def delay(msec): time.sleep(msec / 1000.0)