class TechModules(cdl_desc.Modules):
name = "tech"
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("tech_sync_bit")]
modules += [CdlModule("tech_sync_flop")]
pass
class ApbModules(cdl_desc.Modules):
name = "apb"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True, "apb":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("apb_target_i2c_master") ]
modules += [ CdlModule("i2c_slave_apb_master") ]
modules += [ CdlModule("tb_apb_target_i2c", src_dir=tb_src_dir) ]
pass
class TimerModules(cdl_desc.Modules):
name = "clock_timer"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("clock_timer")]
modules += [CdlModule("clock_timer_async")]
modules += [CdlModule("clock_timer_as_sec_nsec")]
pass
class I2CModules(cdl_desc.Modules):
name = "i2c"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("i2c_interface") ]
modules += [ CdlModule("i2c_master") ]
modules += [ CdlModule("i2c_slave") ]
pass
class JtagModules(cdl_desc.Modules):
name = "jtag"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True, "apb": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("jtag_tap")]
modules += [CdlModule("jtag_tap_apb")]
modules += [CdlModule("apb_target_jtag")]
modules += [CdlModule("tb_jtag_apb_timer", src_dir=tb_src_dir)]
pass
class DE1Modules(cdl_desc.Modules):
name = "de1"
libraries = {"std":True, "apb":True, "video":True, "utils":True, "io":True, "de1":True}
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("bbc_micro_de1_cl") ]
modules += [ CdlModule("bbc_micro_de1_cl_io") ]
modules += [ CdlModule("bbc_micro_de1_cl_bbc") ]
pass
class FramebufferModules(cdl_desc.Modules):
name = "framebuffer"
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"apb":True, "std":True, "utils":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ FramebufferTimingCdl("framebuffer_timing") ]
modules += [ FramebufferTeletextCdl("framebuffer_teletext") ]
modules += [ CdlModule("framebuffer") ]
modules += [ CdlModule("tb_framebuffer_timing", src_dir=tb_src_dir) ]
pass
class SimpleModules(cdl_desc.Modules):
name = "simple"
src_dir = "tests/simple"
modules = []
modules += [CdlModule("tie_high")]
modules += [CdlModule("tie_both")]
modules += [CdlModule("toggle")]
modules += [CdlModule("invert")]
modules += [CdlModule("and")]
modules += [CdlModule("invert_chain")]
modules += [CdlModule("constants")]
modules += [CdlModule("mux")]
modules += [CdlModule("alu")]
modules += [CdlModule("mux_array")]
pass
class SubsystemModules(cdl_desc.Modules):
"""
Instantiation of a pipeline + control, debug, coprocessors,
and trace, with 64kB SRAM and APB master interface
"""
name = "subsystems"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("reve_r_subsystem_3") ]
modules += [ CdlModule("reve_r_subsystem_5") ]
pass
class CoreModules(cdl_desc.Modules):
"""
These are processing modules used by the pipelines
"""
name = "core"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("reve_r_alu") ]
modules += [ CdlModule("reve_r_muldiv") ]
modules += [ CdlModule("reve_r_dmem_request") ]
modules += [ CdlModule("reve_r_dmem_read_data") ]
pass
class PipelineModules(cdl_desc.Modules):
"""
These are pipeline instances that use the decode, csrs and core modules
They must be controlled by pipeline_control modules
"""
name = "pipeline"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
# The following includes decode (which is based on mode configs), and has a disableable compressed and coprocessor and e mode
modules += [ CdlModule("reve_r_pipeline_dem_w") ]
modules += [ CdlModule("reve_r_pipeline_d_e_m_w") ]
pass
class PrngiModules(cdl_desc.Modules):
name = "prng"
src_dir = "cdl/prng"
tb_src_dir = "tb_cdl"
libraries = {"std": True, "apb": True}
cdl_include_dirs = ["cdl", "cdl/prng"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("prng_whiteness_monitor")]
modules += [CdlModule("prng_entropy_mux_4")]
modules += [CdlModule("prng")]
modules += [
CdlModule("apb_target_prng", constants={"cfg_disable_whiteness": 0})
]
modules += [CdlModule("tb_prng", src_dir=tb_src_dir)]
pass
class Axi4sModules(cdl_desc.Modules):
name = "axi4s"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True, "utils":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("axi4s32_fifo_4",
force_includes=["axi4s.h"],
types={"gt_generic_valid_req":"t_axi4s32"},
cdl_module_name="generic_valid_ack_fifo",
instance_types={"fifo_status":"fifo_status_7"},
) ]
modules += [ CdlModule("apb_target_axi4s") ]
modules += [ CdlModule("tb_apb_target_axi4s", src_dir="tb_cdl") ]
pass
class TraceModules(cdl_desc.Modules):
"""
The trace modules supply a standard interface out to provide trace information.
There is also a simple standard trace compression supported.
"""
name = "trace"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("reve_r_trace") ]
modules += [ CdlModule("reve_r_trace_pack") ]
modules += [ CdlModule("reve_r_trace_compression") ]
modules += [ CdlModule("reve_r_trace_decompression") ]
pass
class AnalyzerModules(cdl_desc.Modules):
name = "analyzer"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("analyzer_mux_2")]
modules += [
CdlModule("analyzer_mux_8_e",
cdl_filename="analyzer_mux_8",
constants={"analyzer_config_num_targets": 2})
]
modules += [CdlModule("analyzer_mux_8")]
modules += [CdlModule("analyzer_target")]
modules += [CdlModule("analyzer_target_stub")]
pass
class DecodeModules(cdl_desc.Modules):
"""
The instruction decode modules provide decode of RISC-V instructions (i32, i32c)
"""
name = "decode"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
# The following use reve_r_csrs_decode - so a specific instance could be selected based on config
modules += [ CdlModule("reve_r_i32_decode") ]
modules += [ CdlModule("reve_r_e32_decode", cdl_filename="reve_r_i32_decode", constants={"rv_cfg_e32_force_enable":1}) ]
modules += [ CdlModule("reve_r_i32c_decode") ]
modules += [ CdlModule("reve_r_e32c_decode", cdl_filename="reve_r_i32c_decode", constants={"rv_cfg_e32_force_enable":1}) ]
# modules += [ CdlModule("reve_r_debug_decode") ] This has been removed; the code is in i32_decode
pass
class StructModules(cdl_desc.Modules):
name = "struct"
src_dir = "tests/struct"
modules = []
modules += [
CdlModule("generic_fifo_word",
cdl_filename="generic_fifo",
types={"gt_fifo_content": "t_fifo_content_word"})
] # force_includes=["dprintf.h"]
modules += [
CdlModule("generic_fifo_struct",
cdl_filename="generic_fifo",
types={"gt_fifo_content": "t_fifo_content_struct"})
] # force_includes=["dprintf.h"]
modules += [
CdlModule("generic_fifo_hierarchy",
cdl_filename="generic_fifo",
types={"gt_fifo_content": "t_fifo_content_hierarchy"})
] # force_includes=["dprintf.h"]
class ApbTargetModules(cdl_desc.Modules):
name = "apb_target"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True, "apb": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("apb_target_analyzer")]
pass
class ClockingModules(cdl_desc.Modules):
name = "clocking"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("clocking_eye_tracking")]
modules += [CdlModule("clocking_phase_measure")]
modules += [CdlModule("tb_clocking", src_dir=tb_src_dir)]
modules += [CdlModule("tb_clock_timer", src_dir=tb_src_dir)]
# Without cwv: Ran 12 tests in 94.743s :real 1m34.834s: user: 1m17.309s sys 0m49.748s
# With cwv: Ran 12 tests in 87.201s :real 1m27.292s: user: 1m7.740s sys 0m51.569s
# modules += [ CdlSimVerilatedModule("cwv__tb_clock_timer",
# cdl_filename="tb_clock_timer",
# src_dir=tb_src_dir,
# verilog_filename="tb_clock_timer",
# # extra_verilog=["../std/srw_srams.v", "../std/mrw_srams.v"]
# ) ]
pass
class TeletextModules(cdl_desc.Modules):
name = "teletext"
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"apb":True, "std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
# saa5050 needs t_bbc_micro_sram_request
# modules += [ CdlModule("saa5050") ]
modules += [ CdlModule("teletext",constants={"flashing_on_count":10,"max_flashing_count":40}) ]
pass
class VerilogModules(cdl_desc.Modules):
modules: List[cdl_desc.Module]
name = "verilog"
src_dir = "tests/verilog"
modules = []
modules += [Verilog("srw_rams")]
modules += [CModel("rams")]
modules += [CdlModule("ram_burst")]
modules += [Verilog("ram_burst_v")]
modules += [
CdlSimVerilatedModule("ram_burst_v",
cdl_filename="ram_burst",
registered_name="ram_burst",
extra_verilog=["srw_rams.v"])
]
class KasumiModules(cdl_desc.Modules):
name = "kasumi"
src_dir = "cdl/kasumi"
tb_src_dir = "tb_cdl"
libraries = {"std": True}
cdl_include_dirs = ["cdl/kasumi"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("kasumi_fi")]
modules += [CdlModule("kasumi_fo_cycles_3")]
modules += [CdlModule("kasumi_sbox7")]
modules += [CdlModule("kasumi_sbox9")]
modules += [CdlModule("kasumi_cipher_3")]
modules += [CdlModule("tb_kasumi_cipher", src_dir=tb_src_dir)]
pass
class BBCChips(cdl_desc.Modules):
name = "bbc"
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True, "apb":True, "video":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("fdc8271") ]
modules += [ CdlModule("acia6850") ]
modules += [ CdlModule("via6522") ]
modules += [ CdlModule("crtc6845") ]
modules += [ CdlModule("saa5050") ]
modules += [ CdlModule("cpu6502") ]
pass
class CSRModules(cdl_desc.Modules):
"""
These are CSR modules, which implement the decode of CSRs (which could be expanded by a user) and the CSRs themselves.
The configuration of the CSR modules depends on the mode supported - for example, some CSRs do not exist in some configurations
"""
name = "csr"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("reve_r_csrs") ]
# modules += [ CdlModule("reve_r_csrs_machine_only", cdl_filename="reve_r_csrs", constants=reve_r_machine_constants) ]
# modules += [ CdlModule("reve_r_csrs_machine_debug", cdl_filename="reve_r_csrs", constants=reve_r_md_constants) ]
# modules += [ CdlModule("reve_r_csrs_machine_debug_user", cdl_filename="reve_r_csrs", constants=reve_r_mdu_constants) ]
# modules += [ CdlModule("reve_r_csrs_machine_debug_user_irq", cdl_filename="reve_r_csrs", constants=reve_r_mdui_constants) ]
# The decode modules are also configured by machine, debug, user etc enable; numerous modules should be built, probably
# modules += [ CdlModule("reve_r_csrs_decode") ]
pass
class PipelineControlModules(cdl_desc.Modules):
"""
"""
name = "pipeline_control"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std":True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [ src_dir ]
modules = []
modules += [ CdlModule("reve_r_pipeline_control") ]
modules += [ CdlModule("reve_r_pipeline_control_fetch_req") ]
modules += [ CdlModule("reve_r_pipeline_control_fetch_data") ]
modules += [ CdlModule("reve_r_pipeline_control_flow") ]
modules += [ CdlModule("reve_r_pipeline_trap_interposer") ]
modules += [ CdlModule("reve_r_pipeline_debug") ]
pass
class VCU108Modules(cdl_desc.Modules):
name = "vcu108"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True, "apb": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [CdlModule("subsys_minimal")]
modules += [CdlModule("vcu108_debug")]
modules += [
CdlModule(
"vcu108_riscv",
instance_types={"riscv_i32_minimal_generic": "riscv_i32_minimal"},
cdl_filename="vcu108_riscv_generic")
]
modules += [
CdlModule(
"vcu108_riscv_3",
instance_types={"riscv_i32_minimal_generic": "riscv_i32_minimal3"},
cdl_filename="vcu108_riscv_generic")
]
modules += [
CdlModule("tb_vcu108_debug",
instance_types={"vcu108_generic": "vcu108_debug"},
cdl_filename="tb_vcu108_generic",
src_dir=tb_src_dir)
]
modules += [
CdlModule("tb_vcu108_riscv",
instance_types={"vcu108_generic": "vcu108_riscv"},
cdl_filename="tb_vcu108_generic",
src_dir=tb_src_dir)
]
modules += [
CdlModule("tb_vcu108_riscv_3",
instance_types={"vcu108_generic": "vcu108_riscv_3"},
cdl_filename="tb_vcu108_generic",
src_dir=tb_src_dir)
]
pass
class DprintfModules(cdl_desc.Modules):
name = "dprintf"
c_src_dir = "cmodel"
src_dir = "cdl"
tb_src_dir = "tb_cdl"
libraries = {"std": True}
cdl_include_dirs = ["cdl"]
export_dirs = cdl_include_dirs + [src_dir]
modules = []
modules += [
CdlModule("async_reduce2_4_28_l",
constants={
"input_width": 4,
"output_width": 28,
"shift_right": 0,
"double_sr": 1
},
cdl_filename="generic_async_reduce")
]
modules += [
CdlModule("async_reduce2_4_28_r",
constants={
"input_width": 4,
"output_width": 28,
"shift_right": 1,
"double_sr": 1
},
cdl_filename="generic_async_reduce")
]
modules += [
CdlModule("async_reduce_4_28_l",
constants={
"input_width": 4,
"output_width": 28,
"shift_right": 0,
"double_sr": 0
},
cdl_filename="generic_async_reduce")
]
modules += [
CdlModule("async_reduce_4_28_r",
constants={
"input_width": 4,
"output_width": 28,
"shift_right": 1,
"double_sr": 0
},
cdl_filename="generic_async_reduce")
]
modules += [
CdlModule("async_reduce_4_60_l",
constants={
"input_width": 4,
"output_width": 60,
"shift_right": 0,
"double_sr": 0
},
cdl_filename="generic_async_reduce")
]
modules += [
CdlModule("async_reduce_4_60_r",
constants={
"input_width": 4,
"output_width": 60,
"shift_right": 1,
"double_sr": 0
},
cdl_filename="generic_async_reduce")
]
modules += [CdlModule("dprintf")]
modules += [CdlModule("hysteresis_switch")]
modules += [CdlModule("clock_divider")]
modules += [CdlModule("sram_access_mux_2")]
modules += [
CdlModule("fifo_status_1023",
constants={"fifo_depth_max": 1023},
cdl_filename="fifo_status")
]
modules += [
CdlModule("fifo_status_7",
constants={"fifo_depth_max": 7},
cdl_filename="fifo_status")
]
modules += [
CdlModule("dprintf_2_mux",
force_includes=["dprintf.h"],
types={"gt_generic_valid_req": "t_dprintf_req_2"},
cdl_filename="generic_valid_ack_mux")
]
modules += [
CdlModule("dprintf_4_mux",
force_includes=["dprintf.h"],
types={"gt_generic_valid_req": "t_dprintf_req_4"},
cdl_filename="generic_valid_ack_mux")
]
modules += [
CdlModule("dprintf_2_fifo_4",
force_includes=["dprintf.h"],
types={"gt_generic_valid_req": "t_dprintf_req_2"},
instance_types={"fifo_status": "fifo_status_7"},
constants={"fifo_depth": 3},
cdl_filename="generic_valid_ack_fifo")
]
modules += [
CdlModule(
"dprintf_4_fifo_4",
force_includes=[
"dprintf.h"
], # FIfo module has depth 4 as it has an output register and the FIFO internally of depth 3
types={"gt_generic_valid_req": "t_dprintf_req_4"},
instance_types={"fifo_status": "fifo_status_7"},
constants={"fifo_depth": 3},
cdl_filename="generic_valid_ack_fifo")
]
modules += [
CdlModule("dprintf_4_async",
force_includes=["dprintf.h"],
types={"gt_generic_valid_req": "t_dprintf_req_4"},
cdl_filename="generic_valid_ack_async_slow")
]
modules += [CdlModule("dprintf_4_dp_sram_512")]
modules += [
CdlModule("dprintf_4_fifo_512",
force_includes=["dprintf.h"],
types={"gt_generic_valid_req": "t_dprintf_req_4"},
constants={"fifo_depth": 512},
instance_types={
"fifo_status": "fifo_status_1023",
"generic_valid_ack_dpsram": "dprintf_4_dp_sram_512"
},
cdl_filename="generic_valid_ack_sram_fifo")
]
modules += [CdlModule("tb_dprintf", src_dir=tb_src_dir)]
modules += [CdlModule("tb_dprintf_mux", src_dir=tb_src_dir)]
modules += [CdlModule("tb_hysteresis_switch", src_dir=tb_src_dir)]
pass
class LogModules(cdl_desc.Modules):
name = "log"
src_dir = "tests/log"
modules = []
modules += [CdlModule("lfsr_log_tracker")]
pass
class ClockGateModules(cdl_desc.Modules):
name = "struct"
src_dir = "tests/clock_gate"
modules = []
modules += [CdlModule("gc_simple")]
"""
class VectorModules(cdl_desc.Modules):
name = "vector"
src_dir = "tests/vector"
modules = []
modules += [
CdlModule("vector_toggle__width_16",
constants={"width": 16},
cdl_filename="vector_toggle")
]
modules += [
CdlModule("vector_toggle__width_18",
constants={"width": 18},
cdl_filename="vector_toggle")
]
modules += [
CdlModule("vector_toggle_complex__width_18",
constants={"width": 18},
cdl_filename="vector_toggle_complex")
] #
# , rmr:vector_toggle_complex=vector_toggle__width_18 rim:vector_toggle_complex=complex_cdl_model") ]
modules += [
CdlModule("vector_add__width_4",
constants={"width": 4},
cdl_filename="vector_add")
]
modules += [
CdlModule("vector_add__width_8",
constants={"width": 8},
cdl_filename="vector_add")
]
modules += [
CdlModule("vector_mult_by_11__width_8",
constants={"width": 8},
cdl_filename="vector_mult_by_11")
]
modules += [
CdlModule("vector_reverse__width_8",
constants={"width": 8},
cdl_filename="vector_reverse")
]
modules += [
CdlModule("vector_nest__width_8",
constants={"width": 8},
cdl_filename="vector_nest")
]
modules += [
CdlModule("vector_sum__width_4",
constants={"width": 4},
cdl_filename="vector_sum")
]
modules += [
CdlModule("vector_sum__width_8",
constants={"width": 8},
cdl_filename="vector_sum")
]
modules += [
CdlModule("vector_sum__width_64",
constants={"width": 64},
cdl_filename="vector_sum")
]
modules += [CdlModule("vector_op_1")]
modules += [CdlModule("vector_op_2")]
modules += [
CdlModule("vector_sum_2__width_4",
constants={"width": 4},
cdl_filename="vector_sum_2")
]
modules += [
CdlSimVerilatedModule(
"vector_sum_2__width_4_v",
verilog_filename="vector_sum_2__width_4",
cdl_filename="vector_sum_2",
constants={"width": 4},
)
]
pass