def test_bint(self): # type: () -> None x = Var('x') y = Var('y') z = Var('z') w = Var('w') v = Var('v') u = Var('u') r = Rtl( z << iadd(x, y), w << bint(v), u << iadd(z, w) ) r1 = r.copy({}) s = r.substitution(r1, {}) s[x].set_typevar(TypeVar.singleton(i32.by(8))) s[z].set_typevar(TypeVar.singleton(i32.by(8))) # TODO: Relax this to simd=True s[v].set_typevar(TypeVar('v', '', bools=(1, 1), simd=(8, 8))) r1.cleanup_concrete_rtl() assert s is not None assert s[x].get_typevar().singleton_type() == i32.by(8) assert s[y].get_typevar().singleton_type() == i32.by(8) assert s[z].get_typevar().singleton_type() == i32.by(8) assert s[w].get_typevar().singleton_type() == i32.by(8) assert s[u].get_typevar().singleton_type() == i32.by(8) assert s[v].get_typevar().singleton_type() == b1.by(8)
def setUp(self): # type: () -> None self.v0 = Var("v0") self.v1 = Var("v1") self.v2 = Var("v2") self.v3 = Var("v3") self.v4 = Var("v4") self.v5 = Var("v5") self.v6 = Var("v6") self.v7 = Var("v7") self.v8 = Var("v8") self.v9 = Var("v9") self.imm0 = Var("imm0") self.IxN_nonscalar = TypeVar("IxN_nonscalar", "", ints=True, scalars=False, simd=True) self.TxN = TypeVar("TxN", "", ints=True, bools=True, floats=True, scalars=False, simd=True) self.b1 = TypeVar.singleton(b1)
def test_vselect_icmpimm(self): # type: () -> None x = Var('x') y = Var('y') z = Var('z') w = Var('w') v = Var('v') zeroes = Var('zeroes') imm0 = Var("imm0") r = Rtl( zeroes << iconst(imm0), y << icmp(intcc.eq, x, zeroes), v << vselect(y, z, w), ) r1 = r.copy({}) s = r.substitution(r1, {}) s[zeroes].set_typevar(TypeVar.singleton(i32.by(4))) s[z].set_typevar(TypeVar.singleton(f32.by(4))) r1.cleanup_concrete_rtl() assert s is not None assert s[zeroes].get_typevar().singleton_type() == i32.by(4) assert s[x].get_typevar().singleton_type() == i32.by(4) assert s[y].get_typevar().singleton_type() == b32.by(4) assert s[z].get_typevar().singleton_type() == f32.by(4) assert s[w].get_typevar().singleton_type() == f32.by(4) assert s[v].get_typevar().singleton_type() == f32.by(4)
def test_cleanup_concrete_rtl_ireduce_bad(self): # type: () -> None x = Var('x') y = Var('y') x.set_typevar(TypeVar.singleton(i16.by(1))) r = Rtl( y << ireduce(x), ) with self.assertRaises(AssertionError): r.cleanup_concrete_rtl()
def test_cleanup_concrete_rtl_ireduce(self): # type: () -> None x = Var('x') y = Var('y') r = Rtl( y << ireduce(x), ) r1 = r.copy({}) s = r.substitution(r1, {}) s[x].set_typevar(TypeVar.singleton(i8.by(2))) r1.cleanup_concrete_rtl() assert s is not None assert s[x].get_typevar().singleton_type() == i8.by(2) assert s[y].get_typevar().singleton_type() == i8.by(2)
def test_cleanup_concrete_rtl(self): # type: () -> None typ = i64.by(4) x = Var('x') lo = Var('lo') hi = Var('hi') r = Rtl( (lo, hi) << vsplit(x), ) r1 = r.copy({}) s = r.substitution(r1, {}) s[x].set_typevar(TypeVar.singleton(typ)) r1.cleanup_concrete_rtl() assert s is not None assert s[x].get_typevar().singleton_type() == typ assert s[lo].get_typevar().singleton_type() == i64.by(2) assert s[hi].get_typevar().singleton_type() == i64.by(2)
""" Supplementary instruction definitions for Intel. This module defines additional instructions that are useful only to the Intel target ISA. """ from cdsl.operands import Operand from cdsl.typevar import TypeVar from cdsl.instructions import Instruction, InstructionGroup GROUP = InstructionGroup("x86", "Intel-specific instruction set") iWord = TypeVar('iWord', 'A scalar integer machine word', ints=(32, 64)) nlo = Operand('nlo', iWord, doc='Low part of numerator') nhi = Operand('nhi', iWord, doc='High part of numerator') d = Operand('d', iWord, doc='Denominator') q = Operand('q', iWord, doc='Quotient') r = Operand('r', iWord, doc='Remainder') udivmodx = Instruction('x86_udivmodx', r""" Extended unsigned division. Concatenate the bits in `nhi` and `nlo` to form the numerator. Interpret the bits as an unsigned number and divide by the unsigned denominator `d`. Trap when `d` is zero or if the quotient is larger than the range of the output. Return both quotient and remainder.
Useful semantics "macro" instructions built on top of the primitives. """ from __future__ import absolute_import from cdsl.operands import Operand from cdsl.typevar import TypeVar from cdsl.instructions import Instruction, InstructionGroup from base.types import b1 from base.immediates import imm64 from cdsl.ast import Var from cdsl.xform import Rtl from semantics.primitives import bv_from_imm64, bvite import base.formats # noqa GROUP = InstructionGroup("primitive_macros", "Semantic macros instruction set") AnyBV = TypeVar('AnyBV', bitvecs=True, doc="") x = Var('x') y = Var('y') imm = Var('imm') a = Var('a') # # Bool-to-bv1 # BV1 = TypeVar("BV1", bitvecs=(1, 1), doc="") bv1_op = Operand('bv1_op', BV1, doc="") cond_op = Operand("cond", b1, doc="") bool2bv = Instruction('bool2bv', r"""Convert a b1 value to a 1-bit BV""", ins=cond_op, outs=bv1_op)
This module defines a primitive instruction set, in terms of which the base set is described. Most instructions in this set correspond 1-1 with an SMTLIB bitvector function. """ from __future__ import absolute_import from cdsl.operands import Operand from cdsl.typevar import TypeVar from cdsl.instructions import Instruction, InstructionGroup from cdsl.ti import WiderOrEq from base.types import b1 from base.immediates import imm64 import base.formats # noqa GROUP = InstructionGroup("primitive", "Primitive instruction set") BV = TypeVar('BV', 'A bitvector type.', bitvecs=True) BV1 = TypeVar('BV1', 'A single bit bitvector.', bitvecs=(1, 1)) Real = TypeVar('Real', 'Any real type.', ints=True, floats=True, bools=True, simd=True) x = Operand('x', BV, doc="A semantic value X") y = Operand('x', BV, doc="A semantic value Y (same width as X)") a = Operand('a', BV, doc="A semantic value A (same width as X)") cond = Operand('b', TypeVar.singleton(b1), doc='A b1 value') real = Operand('real', Real, doc="A real cranelift value") fromReal = Operand('fromReal',
from cdsl.ti import WiderOrEq from base.types import b1 from base.immediates import imm64 import base.formats # noqa GROUP = InstructionGroup("primitive", "Primitive instruction set") BV = TypeVar('BV', 'A bitvector type.', bitvecs=True) BV1 = TypeVar('BV1', 'A single bit bitvector.', bitvecs=(1, 1)) Real = TypeVar('Real', 'Any real type.', ints=True, floats=True, bools=True, simd=True) x = Operand('x', BV, doc="A semantic value X") y = Operand('x', BV, doc="A semantic value Y (same width as X)") a = Operand('a', BV, doc="A semantic value A (same width as X)") cond = Operand('b', TypeVar.singleton(b1), doc='A b1 value') real = Operand('real', Real, doc="A real cretonne value") fromReal = Operand('fromReal', Real.to_bitvec(), doc="A real cretonne value converted to a BV") # # BV Conversion/Materialization # prim_to_bv = Instruction( 'prim_to_bv', r""" Convert an SSA Value to a flat bitvector """, ins=(real), outs=(fromReal)) prim_from_bv = Instruction(
This module defines the basic Cretonne instruction set that all targets support. """ from __future__ import absolute_import from cdsl.operands import Operand, VARIABLE_ARGS from cdsl.typevar import TypeVar from cdsl.instructions import Instruction, InstructionGroup from base.types import i8, f32, f64, b1 from base.immediates import imm64, uimm8, ieee32, ieee64, immvector from base.immediates import intcc, floatcc from base import entities import base.formats # noqa GROUP = InstructionGroup("base", "Shared base instruction set") Int = TypeVar('Int', 'A scalar or vector integer type', ints=True, simd=True) iB = TypeVar('iB', 'A scalar integer type', ints=True) iAddr = TypeVar('iAddr', 'An integer address type', ints=(32, 64)) Testable = TypeVar('Testable', 'A scalar boolean or integer type', ints=True, bools=True) TxN = TypeVar('TxN', 'A SIMD vector type', ints=True, floats=True, bools=True, scalars=False, simd=True) Any = TypeVar('Any', 'Any integer, float, or boolean scalar or vector type',