def test_failure_from_system_task(dut):
"""Allow the dut to call $fail_test() from verilog"""
clock = Clock(dut.clk, 100)
clock.start()
coro = cocotb.fork(clock_mon(dut))
extern = cocotb.fork(run_external(dut))
yield Timer(10000000)
def test_clock_with_units(dut):
clk_1mhz = Clock(dut.clk, 1.0, units='us')
clk_250mhz = Clock(dut.clk, 4.0, units='ns')
if str(clk_1mhz) != "Clock(1.0 MHz)":
raise TestFailure("{} != 'Clock(1.0 MHz)'".format(str(clk_1mhz)))
else:
dut._log.info('Created clock >{}<'.format(str(clk_1mhz)))
if str(clk_250mhz) != "Clock(250.0 MHz)":
raise TestFailure("{} != 'Clock(250.0 MHz)'".format(str(clk_250mhz)))
else:
dut._log.info('Created clock >{}<'.format(str(clk_250mhz)))
clk_gen = cocotb.fork(clk_1mhz.start())
start_time_ns = get_sim_time(units='ns')
yield Timer(1)
yield RisingEdge(dut.clk)
edge_time_ns = get_sim_time(units='ns')
if not isclose(edge_time_ns, start_time_ns + 1000.0):
raise TestFailure("Expected a period of 1 us")
start_time_ns = edge_time_ns
yield RisingEdge(dut.clk)
edge_time_ns = get_sim_time(units='ns')
if not isclose(edge_time_ns, start_time_ns + 1000.0):
raise TestFailure("Expected a period of 1 us")
clk_gen.kill()
clk_gen = cocotb.fork(clk_250mhz.start())
start_time_ns = get_sim_time(units='ns')
yield Timer(1)
yield RisingEdge(dut.clk)
edge_time_ns = get_sim_time(units='ns')
if not isclose(edge_time_ns, start_time_ns + 4.0):
raise TestFailure("Expected a period of 4 ns")
start_time_ns = edge_time_ns
yield RisingEdge(dut.clk)
edge_time_ns = get_sim_time(units='ns')
if not isclose(edge_time_ns, start_time_ns + 4.0):
raise TestFailure("Expected a period of 4 ns")
clk_gen.kill()
def verif_pulse(dut):
dut.select_input_i <= 0
dut.data1_i <= 0
dut.data2_i <= 0
dut.data_en_i <= 0
dut.data_sof_i <= 0
dut.data_eof_i <= 0
dut.start_acquisition_i <= 0
dut.prescaler_i <= 0
dut.update_presc_i <= 0
dut.start_i <= 0
dut.trig_i <= 0
dut.dflt_val_i <= 0
dut.period_cnt_i <= 50
dut.duty_cnt_i <= 10
dut.enable_i <= 0
reset_n = dut.rst_i
cocotb.fork(Clock(dut.clk_i, 10, 'ns').start())
yield reset_dut(reset_n, dut.clk_i, 500)
dut._log.debug("After reset")
# now correct behavior
yield RisingEdge(dut.clk_i)
dut.update_presc_i <= 1
dut.prescaler_i <= 2
yield RisingEdge(dut.clk_i)
dut.update_presc_i <= 0
yield RisingEdge(dut.clk_i)
dut.select_input_i <= 2
yield RisingEdge(dut.clk_i)
# start dataToRam
dut.start_acquisition_i <= 1
yield RisingEdge(dut.clk_i)
dut.start_acquisition_i <= 0
yield RisingEdge(dut.clk_i)
# start pseudoGen
dut.start_i <= 1
yield RisingEdge(dut.clk_i)
yield RisingEdge(dut.clk_i)
# start pulseDelay
dut.enable_i <= 1
for i in range(0, 10):
yield RisingEdge(dut.clk_i)
dut.enable_i <= 0
yield RisingEdge(dut.clk_i)
#yield RisingEdge(dut.m_axis_tlast)
yield RisingEdge(dut.clk_i)
for i in range(0, 40):
yield RisingEdge(dut.clk_i)
yield RisingEdge(dut.clk_i)
# reconfigure pseudoGen and start dataToRam
dut.dflt_val_i <= 100
dut.start_acquisition_i <= 1
yield RisingEdge(dut.clk_i)
dut.start_acquisition_i <= 0
# restart pulseDelay
yield RisingEdge(dut.clk_i)
dut.enable_i <= 1
for i in range(0, 10):
yield RisingEdge(dut.clk_i)
dut.enable_i <= 0
yield RisingEdge(dut.clk_i)
#yield RisingEdge(dut.m_axis_tlast)
yield RisingEdge(dut.clk_i)
for i in range(0, 40):
yield RisingEdge(dut.clk_i)
def test_sume_event_switch(dut):
"""Test to make sure that event_output_queues module is working properly.
"""
# start HW sim clock
cocotb.fork(Clock(dut.axis_aclk, PERIOD).start())
yield reset_dut(dut)
yield ClockCycles(dut.axis_aclk, START_DELAY)
# read the pkts and rank values
pkts_in_0, meta_in_0 = make_pkts_meta_in(0b00000001)
pkts_in_1, meta_in_1 = make_pkts_meta_in(0b00000100)
pkts_in_2, meta_in_2 = make_pkts_meta_in(0b00010000)
pkts_in_3, meta_in_3 = make_pkts_meta_in(0b01000000)
# Attach an AXI4Stream Master to the input pkt interface
pkt_master_0 = AXI4StreamMaster(dut, 's_axis_0', dut.axis_aclk)
pkt_master_1 = AXI4StreamMaster(dut, 's_axis_1', dut.axis_aclk)
pkt_master_2 = AXI4StreamMaster(dut, 's_axis_2', dut.axis_aclk)
pkt_master_3 = AXI4StreamMaster(dut, 's_axis_3', dut.axis_aclk)
# Attach an AXI4StreamSlave to the output pkt interface
pkt_slave_0 = AXI4StreamSlave(dut,
'm_axis_0',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
pkt_slave_1 = AXI4StreamSlave(dut,
'm_axis_1',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
pkt_slave_2 = AXI4StreamSlave(dut,
'm_axis_2',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
pkt_slave_3 = AXI4StreamSlave(dut,
'm_axis_3',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
# start reading for pkts
pkt_slave_thread_0 = cocotb.fork(
pkt_slave_0.read_n_pkts(len(pkts_in_0), log_raw=True))
pkt_slave_thread_1 = cocotb.fork(
pkt_slave_1.read_n_pkts(len(pkts_in_1), log_raw=True))
pkt_slave_thread_2 = cocotb.fork(
pkt_slave_2.read_n_pkts(len(pkts_in_2), log_raw=True))
pkt_slave_thread_3 = cocotb.fork(
pkt_slave_3.read_n_pkts(len(pkts_in_3), log_raw=True))
# Send pkts and metadata in the HW sim
rate = 1.0 * INGRESS_LINK_RATE * 5 / 8.0 # bytes/cycle
pkt_master_thread_0 = cocotb.fork(
pkt_master_0.write_pkts(pkts_in_0, meta_in_0, rate=rate))
pkt_master_thread_1 = cocotb.fork(
pkt_master_1.write_pkts(pkts_in_1, meta_in_1, rate=rate))
pkt_master_thread_2 = cocotb.fork(
pkt_master_2.write_pkts(pkts_in_2, meta_in_2, rate=rate))
pkt_master_thread_3 = cocotb.fork(
pkt_master_3.write_pkts(pkts_in_3, meta_in_3, rate=rate))
yield pkt_master_thread_0.join()
yield pkt_master_thread_1.join()
yield pkt_master_thread_2.join()
yield pkt_master_thread_3.join()
# Wait for the pkt_slave to finish (or timeout)
yield pkt_slave_thread_0.join()
yield pkt_slave_thread_1.join()
yield pkt_slave_thread_2.join()
yield pkt_slave_thread_3.join()
# pkts_out = pkt_slave.pkts
# meta_out = pkt_slave.metadata
yield ClockCycles(dut.axis_aclk, 20)
def test_external_that_yields(dut):
clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
value = yield external(test_ext_function_access)(dut)
def test_multiple_externals(dut):
clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
value = yield external(test_ext_function)(dut)
dut._log.info("First one completed")
value = yield external(test_ext_function)(dut)
dut._log.info("Second one completed")
def __init__(self, dut):
self.dut = dut
self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE"))
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = UltraScalePlusPcieDevice(
# configuration options
pcie_generation=3,
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
rc_4tlp_straddle=False,
enable_pf1=False,
enable_client_tag=True,
enable_extended_tag=True,
enable_parity=False,
enable_rx_msg_interface=False,
enable_sriov=False,
enable_extended_configuration=False,
enable_pf0_msi=True,
enable_pf1_msi=False,
# signals
# Clock and Reset Interface
user_clk=dut.clk_250mhz,
user_reset=dut.rst_250mhz,
# user_lnk_up
# sys_clk
# sys_clk_gt
# sys_reset
# phy_rdy_out
# Requester reQuest Interface
rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
# pcie_rq_tag0
# pcie_rq_tag1
# pcie_rq_tag_av
# pcie_rq_tag_vld0
# pcie_rq_tag_vld1
# Requester Completion Interface
rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
# Completer reQuest Interface
cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
# pcie_cq_np_req
# pcie_cq_np_req_count
# Completer Completion Interface
cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=dut.cfg_mgmt_addr,
cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
cfg_mgmt_write=dut.cfg_mgmt_write,
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
cfg_mgmt_read=dut.cfg_mgmt_read,
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
# cfg_mgmt_debug_access
# Configuration Status Interface
# cfg_phy_link_down
# cfg_phy_link_status
# cfg_negotiated_width
# cfg_current_speed
cfg_max_payload=dut.cfg_max_payload,
cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status
# cfg_vf_status
# cfg_function_power_state
# cfg_vf_power_state
# cfg_link_power_state
# cfg_err_cor_out
# cfg_err_nonfatal_out
# cfg_err_fatal_out
# cfg_local_error_out
# cfg_local_error_valid
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable
# cfg_tph_st_mode
# cfg_vf_tph_requester_enable
# cfg_vf_tph_st_mode
# Configuration Received Message Interface
# cfg_msg_received
# cfg_msg_received_data
# cfg_msg_received_type
# Configuration Transmit Message Interface
# cfg_msg_transmit
# cfg_msg_transmit_type
# cfg_msg_transmit_data
# cfg_msg_transmit_done
# Configuration Flow Control Interface
cfg_fc_ph=dut.cfg_fc_ph,
cfg_fc_pd=dut.cfg_fc_pd,
cfg_fc_nph=dut.cfg_fc_nph,
cfg_fc_npd=dut.cfg_fc_npd,
cfg_fc_cplh=dut.cfg_fc_cplh,
cfg_fc_cpld=dut.cfg_fc_cpld,
cfg_fc_sel=dut.cfg_fc_sel,
# Configuration Control Interface
# cfg_hot_reset_in
# cfg_hot_reset_out
# cfg_config_space_enable
# cfg_dsn
# cfg_bus_number
# cfg_ds_port_number
# cfg_ds_bus_number
# cfg_ds_device_number
# cfg_ds_function_number
# cfg_power_state_change_ack
# cfg_power_state_change_interrupt
cfg_err_cor_in=dut.status_error_cor,
cfg_err_uncor_in=dut.status_error_uncor,
# cfg_flr_in_process
# cfg_flr_done
# cfg_vf_flr_in_process
# cfg_vf_flr_func_num
# cfg_vf_flr_done
# cfg_pm_aspm_l1_entry_reject
# cfg_pm_aspm_tx_l0s_entry_disable
# cfg_req_pm_transition_l23_ready
# cfg_link_training_enable
# Configuration Interrupt Controller Interface
# cfg_interrupt_int
# cfg_interrupt_sent
# cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=dut.
cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=dut.
cfg_interrupt_msi_pending_status_data_enable,
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
# cfg_interrupt_msix_enable
# cfg_interrupt_msix_mask
# cfg_interrupt_msix_vf_enable
# cfg_interrupt_msix_vf_mask
# cfg_interrupt_msix_address
# cfg_interrupt_msix_data
# cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface
# cfg_ext_read_received
# cfg_ext_write_received
# cfg_ext_register_number
# cfg_ext_function_number
# cfg_ext_write_data
# cfg_ext_write_byte_enable
# cfg_ext_read_data
# cfg_ext_read_data_valid
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver(self.rc)
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0,
2**self.BAR0_APERTURE,
ext=True,
prefetch=True)
# Ethernet
cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 6.4, units="ns").start())
self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0,
dut.qsfp_0_rx_clk_0,
dut.qsfp_0_rx_rst_0)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_0, 6.4, units="ns").start())
self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0,
dut.qsfp_0_tx_clk_0,
dut.qsfp_0_tx_rst_0)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_1, 6.4, units="ns").start())
self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1,
dut.qsfp_0_rx_clk_1,
dut.qsfp_0_rx_rst_1)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_1, 6.4, units="ns").start())
self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1,
dut.qsfp_0_tx_clk_1,
dut.qsfp_0_tx_rst_1)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_2, 6.4, units="ns").start())
self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2,
dut.qsfp_0_rx_clk_2,
dut.qsfp_0_rx_rst_2)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_2, 6.4, units="ns").start())
self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2,
dut.qsfp_0_tx_clk_2,
dut.qsfp_0_tx_rst_2)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_3, 6.4, units="ns").start())
self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3,
dut.qsfp_0_rx_clk_3,
dut.qsfp_0_rx_rst_3)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_3, 6.4, units="ns").start())
self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3,
dut.qsfp_0_tx_clk_3,
dut.qsfp_0_tx_rst_3)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_0, 6.4, units="ns").start())
self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0,
dut.qsfp_1_rx_clk_0,
dut.qsfp_1_rx_rst_0)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_0, 6.4, units="ns").start())
self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0,
dut.qsfp_1_tx_clk_0,
dut.qsfp_1_tx_rst_0)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_1, 6.4, units="ns").start())
self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1,
dut.qsfp_1_rx_clk_1,
dut.qsfp_1_rx_rst_1)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_1, 6.4, units="ns").start())
self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1,
dut.qsfp_1_tx_clk_1,
dut.qsfp_1_tx_rst_1)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_2, 6.4, units="ns").start())
self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2,
dut.qsfp_1_rx_clk_2,
dut.qsfp_1_rx_rst_2)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_2, 6.4, units="ns").start())
self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2,
dut.qsfp_1_tx_clk_2,
dut.qsfp_1_tx_rst_2)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_3, 6.4, units="ns").start())
self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3,
dut.qsfp_1_rx_clk_3,
dut.qsfp_1_rx_rst_3)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_3, 6.4, units="ns").start())
self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3,
dut.qsfp_1_tx_clk_3,
dut.qsfp_1_tx_rst_3)
dut.user_sw.setimmediatevalue(0)
dut.qsfp_0_rx_error_count_0.setimmediatevalue(0)
dut.qsfp_0_rx_error_count_1.setimmediatevalue(0)
dut.qsfp_0_rx_error_count_2.setimmediatevalue(0)
dut.qsfp_0_rx_error_count_3.setimmediatevalue(0)
dut.qsfp_1_rx_error_count_0.setimmediatevalue(0)
dut.qsfp_1_rx_error_count_1.setimmediatevalue(0)
dut.qsfp_1_rx_error_count_2.setimmediatevalue(0)
dut.qsfp_1_rx_error_count_3.setimmediatevalue(0)
dut.qsfp_0_modprs_l.setimmediatevalue(0)
dut.qsfp_1_modprs_l.setimmediatevalue(0)
dut.qsfp_int_l.setimmediatevalue(1)
dut.qsfp_i2c_scl_i.setimmediatevalue(1)
dut.qsfp_i2c_sda_i.setimmediatevalue(1)
dut.eeprom_i2c_scl_i.setimmediatevalue(1)
dut.eeprom_i2c_sda_i.setimmediatevalue(1)
dut.qspi_0_dq_i.setimmediatevalue(0)
dut.qspi_1_dq_i.setimmediatevalue(0)
self.loopback_enable = False
cocotb.fork(self._run_loopback())
def setup_function(dut, key, iv):
cocotb.fork(Clock(dut.clk, CLK_PERIOD).start())
dut.rst = 0
dut.key = key
dut.iv = iv
dut.next_data = 0
async def test_14_sequences(dut):
"""Tests the Sequences"""
clock = Clock(dut.clk, 2, units="us")
cocotb.fork(clock.start())
await run_tests(dut)
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2.56, units="ns").start())
# Ethernet
cocotb.fork(Clock(dut.phy_gmii_clk, 8, units="ns").start())
self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er,
dut.phy_gmii_rx_dv, dut.phy_gmii_clk,
dut.phy_gmii_rst, dut.phy_gmii_clk_en)
self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er,
dut.phy_gmii_tx_en, dut.phy_gmii_clk,
dut.phy_gmii_rst, dut.phy_gmii_clk_en)
dut.phy_gmii_clk_en.setimmediatevalue(1)
cocotb.fork(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1,
dut.qsfp1_rx_clk_1,
dut.qsfp1_rx_rst_1)
cocotb.fork(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1,
dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
cocotb.fork(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2,
dut.qsfp1_rx_clk_2,
dut.qsfp1_rx_rst_2)
cocotb.fork(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2,
dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
cocotb.fork(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3,
dut.qsfp1_rx_clk_3,
dut.qsfp1_rx_rst_3)
cocotb.fork(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3,
dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
cocotb.fork(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4,
dut.qsfp1_rx_clk_4,
dut.qsfp1_rx_rst_4)
cocotb.fork(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4,
dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
cocotb.fork(Clock(dut.qsfp2_rx_clk_1, 2.56, units="ns").start())
self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1,
dut.qsfp2_rx_clk_1,
dut.qsfp2_rx_rst_1)
cocotb.fork(Clock(dut.qsfp2_tx_clk_1, 2.56, units="ns").start())
self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1,
dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1)
cocotb.fork(Clock(dut.qsfp2_rx_clk_2, 2.56, units="ns").start())
self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2,
dut.qsfp2_rx_clk_2,
dut.qsfp2_rx_rst_2)
cocotb.fork(Clock(dut.qsfp2_tx_clk_2, 2.56, units="ns").start())
self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2,
dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2)
cocotb.fork(Clock(dut.qsfp2_rx_clk_3, 2.56, units="ns").start())
self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3,
dut.qsfp2_rx_clk_3,
dut.qsfp2_rx_rst_3)
cocotb.fork(Clock(dut.qsfp2_tx_clk_3, 2.56, units="ns").start())
self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3,
dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3)
cocotb.fork(Clock(dut.qsfp2_rx_clk_4, 2.56, units="ns").start())
self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4,
dut.qsfp2_rx_clk_4,
dut.qsfp2_rx_rst_4)
cocotb.fork(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start())
self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4,
dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4)
dut.btnu.setimmediatevalue(0)
dut.btnl.setimmediatevalue(0)
dut.btnd.setimmediatevalue(0)
dut.btnr.setimmediatevalue(0)
dut.btnc.setimmediatevalue(0)
dut.sw.setimmediatevalue(0)
dut.uart_rxd.setimmediatevalue(0)
dut.uart_cts.setimmediatevalue(0)
def test_slow_egress(dut):
"""Testing the simple_tm module with a constant fill level
"""
# start HW sim clock
cocotb.fork(Clock(dut.axis_aclk, PERIOD).start())
# Reset the DUT
dut._log.debug("Resetting DUT")
dut.axis_resetn <= 0
yield ClockCycles(dut.axis_aclk, 10)
dut.axis_resetn <= 1
dut._log.debug("Out of reset")
# wait for the pifo to finish resetting
yield FallingEdge(dut.axis_aclk)
while dut.simple_tm_inst.pifo_busy.value:
yield RisingEdge(dut.axis_aclk)
yield FallingEdge(dut.axis_aclk)
yield RisingEdge(dut.axis_aclk)
yield ClockCycles(dut.axis_aclk, 100)
dut.m_axis_tready <= 0
# Attach an AXI4Stream Master to the input pkt interface
pkt_master = AXI4StreamMaster(dut, 's_axis', dut.axis_aclk)
# Attach and AXI4StreamSlave to the output pkt interface
pkt_slave = AXI4StreamSlave(dut,
'm_axis',
dut.axis_aclk,
idle_timeout=IDLE_TIMEOUT)
# connect stats tools
pkt_in_stats = AXI4StreamStats(dut,
's_axis',
dut.axis_aclk,
idle_timeout=IDLE_TIMEOUT)
pkt_out_stats = AXI4StreamStats(dut,
'm_axis',
dut.axis_aclk,
idle_timeout=IDLE_TIMEOUT)
# start counter for stats
counter = CycleCounter(dut.axis_aclk)
counter_thread = cocotb.fork(counter.start())
# start recording stats
pkt_in_stats_thread = cocotb.fork(
pkt_in_stats.record_n_start_times(NUM_PKTS, counter))
pkt_out_stats_thread = cocotb.fork(
pkt_out_stats.record_n_start_times(NUM_PKTS, counter))
# start writing pkts
data = make_pkts_and_meta(NUM_PKTS)
pkts_in = [tup[1] for tup in data]
meta_in = [tup[2] for tup in data]
pkt_master_thread = cocotb.fork(pkt_master.write_pkts(pkts_in, meta_in))
# wait a few cycles between samples
for i in range(10):
yield FallingEdge(dut.axis_aclk)
yield RisingEdge(dut.axis_aclk)
expected_ranks = []
for i in range(NUM_PKTS):
# compute expected pkt
input_ranks = [
Metadata(m.get_buff()).rank for m in pkt_in_stats.metadata
]
# print 'input_ranks = {}'.format(input_ranks)
output_ranks = [
Metadata(m.get_buff()).rank for m in pkt_out_stats.metadata
]
# print 'output_ranks = {}'.format(output_ranks)
[input_ranks.remove(r) for r in expected_ranks]
# print 'curr_rank_set = {}'.format(input_ranks)
try:
expected_ranks.append(min(input_ranks))
except ValueError as e:
pass
# print 'expected_ranks = {}'.format(expected_ranks)
# print '======================='
# Read out packet
yield pkt_slave.read_n_pkts(1)
# wait a few cycles between samples
for i in range(10):
yield FallingEdge(dut.axis_aclk)
yield RisingEdge(dut.axis_aclk)
if pkt_slave.error:
print "ERROR: pkt_slave timed out"
break
# get the actual ranks
meta_out = pkt_slave.metadata
actual_ranks = [Metadata(m.get_buff()).rank for m in meta_out]
input_ranks = [Metadata(m.get_buff()).rank for m in pkt_in_stats.metadata]
print 'input_ranks = {}'.format(input_ranks)
print 'expected output ranks = {}'.format(expected_ranks)
print 'actual output ranks = {}'.format(actual_ranks)
error = False
# for (exp_rank, rank, i) in zip(expected_ranks, actual_ranks, range(len(expected_ranks))):
# if exp_rank != rank:
# print 'ERROR: exp_rank ({}) != actual_rank ({}) for pkt {}'.format(exp_rank, rank, i)
# error = True
for r, i in zip(actual_ranks, range(len(actual_ranks))):
try:
input_ranks.remove(r)
except ValueError as e:
print 'ERROR: output rank ({}) not in input set'.format(r)
print e
error = True
if len(input_ranks) > 0:
print 'ERROR: not all ranks removed: {}'.format(input_ranks)
error = True
yield ClockCycles(dut.axis_aclk, 20)
if error:
print 'ERROR: Test Failed'
raise (TestFailure)
async def run_test(dut):
en_gpio_loopback_test = True
en_spi_test = True
clk = Clock(dut.clk, 10, units="ns") # Create a 10us period clock on port clk
cocotb.fork(clk.start()) # Start the clock
dut.uart_txd = 0
await FallingEdge(dut.clk)
### =============================================================================================================
### GPIO LOOPBACK TEST
if en_gpio_loopback_test:
dv = DVTest(dut, "GPIO Loopback", msg_lvl="All")
dv.info("GPIO Loopback Test")
for i in range(20000):
await FallingEdge(dut.clk)
dut.P2_in <= dut.P1_out.value
try:
gpio_value = int(dut.P1_out.value.binstr,2)
loop_done = True if gpio_value == 0xff else False
except ValueError:
gpio_value = 0
loop_done = False
if (i+1) % 1000 == 0:
dv.info("clock = " + str(i+1) +": P1_out = " + str(gpio_value) )
if loop_done: break
await Edge(dut.P1_out)
gpio_result = int(dut.P1_out.value.binstr,2)
dv.eq(gpio_result, 0, "Error count from DUT")
dut.P1_in = 0
await ClockCycles(dut.clk,100)
dv.done()
### =============================================================================================================
### SPI TEST
spi_peripheral = SPIPeripheralMonitor(
dut=dut,
cfg = {
'name' : "SPI Monitor",
'size' : 8, # bits
'mode' : 0,
'lsb_first' : False,
},
io = {
'sclk' : dut.spi_sclk,
'cs_n' : dut.spi_cs,
'sdi' : dut.spi_mosi,
'sdo' : dut.spi_miso,
}
)
# spi_peripheral_expect.append( random.randint(0, 127) )
# spi_peripheral_response.append( random.randint(0, 127) )
if en_spi_test:
dv.info("SPI Test (random modes and speeds)")
spi_n = 15
spi_peripheral_expect = []
spi_scoreboard_expect = []
spi_peripheral_response = []
for i in range(spi_n):
val = i
spi_peripheral_expect.append( val )
spi_scoreboard_expect.append( val )
spi_peripheral_response.append( val )
spi_peripheral.start(spi_peripheral_expect, spi_peripheral_response)
scoreboard = Scoreboard(dut)
scoreboard.add_interface(spi_peripheral, spi_scoreboard_expect, strict_type=False)
random.seed(42)
err_cnt = 0
toggle = 0
for iiii in range(spi_n):
# SEND BYTE-VALUE TO SEND OVER SPI TO Z80 USING BPIO p2[7:0]
dut.P2_in.value = spi_peripheral_expect[iiii]
# SEND MODE AND CLKDIV TO Z80 OVER GPIO P1[7:0]
# Bit [1:0] mode
# Bit [2] toggle (ensure p1_in changes)
# Bit [6:3] clkdiv (div sys clk)
# Bit [7] done
spi_peripheral.mode = random.randrange(4) # i % 4
clkdiv = random.randrange(0, 16, 2)
toggle = (toggle + 4) & 0x04
P1_in = (clkdiv << 3) | toggle | spi_peripheral.mode
dut.P1_in.value = P1_in
# WAIT FOR Z80 TO SEND SPI MESSAGE AND COMPARE WITH EXPECETD VALUE
dv.info("Waiting for SPI Peripheral ({})".format(iiii))
await spi_peripheral.peripheral_monitor()
spi_peripheral.stop()
dut.P1_in.value = 0x80
if err_cnt == 0:
dv.info("SPI Test Passed")
else:
dv.info("SPI Test Failed - Error Count = " + str(err_cnt) )
await ClockCycles(dut.clk,100)
# Print result of scoreboard.
dv.is_true(scoreboard.result, "SPI Test Scoreboard")
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2.56, units="ns").start())
# Ethernet
cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start())
self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_0, 2.56, units="ns").start())
self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_1, 2.56, units="ns").start())
self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_1, 2.56, units="ns").start())
self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_2, 2.56, units="ns").start())
self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_2, 2.56, units="ns").start())
self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2)
cocotb.fork(Clock(dut.qsfp_0_rx_clk_3, 2.56, units="ns").start())
self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3)
cocotb.fork(Clock(dut.qsfp_0_tx_clk_3, 2.56, units="ns").start())
self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_0, 2.56, units="ns").start())
self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_0, 2.56, units="ns").start())
self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_1, 2.56, units="ns").start())
self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_1, 2.56, units="ns").start())
self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_2, 2.56, units="ns").start())
self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_2, 2.56, units="ns").start())
self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2)
cocotb.fork(Clock(dut.qsfp_1_rx_clk_3, 2.56, units="ns").start())
self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3)
cocotb.fork(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start())
self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3)
dut.user_sw.setimmediatevalue(0)
async def test_tile(dut):
clock = Clock(dut.scan_clk, 10000, units="ps")
cocotb.fork(clock.start())
# read param
channel_oneway_width = dut.CHANNEL_ONEWAY_WIDTH.value
ble_num = dut.CLB_BLE_NUM.value
conn_sel_width = dut.CONN_SEL_WIDTH.value
dut._log.info("Found CB with COW: %d, #BLE: %d, CSW: %d" %
(channel_oneway_width, ble_num, conn_sel_width))
# generate and scan in random clb config
lut_binary = [random.randint(0, 1) for i in range(2**channel_oneway_width)]
complete_config = [
random.randint(0, 3) for i in range(channel_oneway_width)
]
# complete_config = [0, 1, 2, 3]
complete_binary = int_list_to_bitstream(complete_config, 3)
is_comb = [1]
clb_bitstream = is_comb + complete_binary + lut_binary
clb_scan_size = len(clb_bitstream)
print("clb bitstream")
print("length: %d" % clb_scan_size)
print(clb_bitstream)
dut.clb_scan_en <= 1
for i in range(clb_scan_size):
dut.clb_scan_in <= clb_bitstream.pop(-1)
await RisingEdge(dut.scan_clk)
dut.clb_scan_en <= 0
# generate and scan in conn config
sb_left_select = [random.randint(0, 2) for i in range(3)]
sb_left_select.append(random.randint(0, 3))
sb_right_select = [random.randint(0, 2) for i in range(3)]
sb_right_select.append(random.randint(0, 3))
sb_top_select = [random.randint(0, 2) for i in range(4)]
sb_bottom_select = [random.randint(0, 2) for i in range(4)]
# convert to bitstream
sb_left_binary = int_list_to_bitstream(sb_left_select, 2)
sb_right_binary = int_list_to_bitstream(sb_right_select, 2)
sb_top_binary = int_list_to_bitstream(sb_top_select, 2)
sb_bottom_binary = int_list_to_bitstream(sb_bottom_select, 2)
# cb config & bitstream
cb_0_config = [random.randint(0, 3) for i in range(2)]
cb_0_binary = int_list_to_bitstream(cb_0_config, 2)
cb_1_config = [random.randint(0, 3) for i in range(2)]
cb_1_binary = int_list_to_bitstream(cb_1_config, 2)
conn_bitstream = sb_left_binary + sb_right_binary + sb_top_binary + sb_bottom_binary + cb_0_binary + cb_1_binary
conn_scan_size = len(conn_bitstream)
print("conn bitstream")
print("length: %d" % conn_scan_size)
print(conn_bitstream)
dut.conn_scan_en <= 1
for i in range(conn_scan_size):
dut.conn_scan_in <= conn_bitstream.pop(-1)
await RisingEdge(dut.scan_clk)
dut.conn_scan_en <= 0
# random input generation
left_in = random.randint(0, 2**channel_oneway_width - 1)
right_in = random.randint(0, 2**channel_oneway_width - 1)
top_in = random.randint(0, 2**channel_oneway_width - 1)
bottom_in = random.randint(0, 2**channel_oneway_width - 1)
left_clb_in = random.randint(0, 1)
bottom_clb_in = random.randint(0, 1)
right_sb_in = random.randint(0, 1)
# input to dut
dut.left_in <= left_in
dut.right_in <= right_in
dut.top_in <= top_in
dut.bottom_in <= bottom_in
dut.left_clb_in <= left_clb_in
dut.bottom_clb_in <= bottom_clb_in
dut.right_sb_in <= right_sb_in
await Timer(100, units='ps')
# verification
# first check if clb out matches lut result
clb_in_actual = dut.test_out_x4.value
clb_in_actual.big_endian = False
clb_out_actual = dut.left_clb_out.value
lut_binary_actual = [
clb_in_actual[complete_config[0]], clb_in_actual[complete_config[1]],
clb_in_actual[complete_config[2]], clb_in_actual[complete_config[3]]
]
lut_in_actual = bin_list_to_int_little_endian(lut_binary_actual)
assert clb_out_actual == lut_binary[
lut_in_actual], "clb out expecting %d, getting %d" % (
lut_binary[lut_in_actual], clb_out_actual)
# check if cb and sb are working properly
# convert int to cocotb BinaryValue for easy bit select
left_in = BinaryValue(left_in, n_bits=4, bigEndian=False)
right_in = BinaryValue(right_in, n_bits=4, bigEndian=False)
top_in = BinaryValue(top_in, n_bits=4, bigEndian=False)
bottom_in = BinaryValue(bottom_in, n_bits=4, bigEndian=False)
# dictionary for finding golden sb out, index is arbitrary arch design
left_out_dict_0 = {0: bottom_in[2], 1: top_in[1], 2: right_in[0]}
left_out_dict_1 = {0: bottom_in[1], 1: top_in[2], 2: right_in[1]}
left_out_dict_2 = {0: bottom_in[0], 1: top_in[3], 2: right_in[2]}
left_out_dict_3 = {
0: bottom_in[3],
1: top_in[0],
2: right_in[3],
3: clb_out_actual.integer
}
right_out_dict_0 = {0: bottom_in[3], 1: top_in[2], 2: left_in[0]}
right_out_dict_1 = {0: bottom_in[0], 1: top_in[1], 2: left_in[1]}
right_out_dict_2 = {0: bottom_in[1], 1: top_in[0], 2: left_in[2]}
right_out_dict_3 = {
0: bottom_in[2],
1: top_in[3],
2: left_in[3],
3: right_sb_in
}
top_out_dict_0 = {0: bottom_in[0], 1: right_in[2], 2: left_in[3]}
top_out_dict_1 = {0: bottom_in[1], 1: right_in[1], 2: left_in[0]}
top_out_dict_2 = {0: bottom_in[2], 1: right_in[0], 2: left_in[1]}
top_out_dict_3 = {0: bottom_in[3], 1: right_in[3], 2: left_in[2]}
bottom_out_dict_0 = {0: top_in[0], 1: right_in[1], 2: left_in[2]}
bottom_out_dict_1 = {0: top_in[1], 1: right_in[2], 2: left_in[1]}
bottom_out_dict_2 = {0: top_in[2], 1: right_in[3], 2: left_in[0]}
bottom_out_dict_3 = {0: top_in[3], 1: right_in[0], 2: left_in[3]}
# create sb golden out
left_out_golden = [
left_out_dict_0[sb_left_select[0]], left_out_dict_1[sb_left_select[1]],
left_out_dict_2[sb_left_select[2]], left_out_dict_3[sb_left_select[3]]
]
right_out_golden = [
right_out_dict_0[sb_right_select[0]],
right_out_dict_1[sb_right_select[1]],
right_out_dict_2[sb_right_select[2]],
right_out_dict_3[sb_right_select[3]]
]
top_out_golden = [
top_out_dict_0[sb_top_select[0]], top_out_dict_1[sb_top_select[1]],
top_out_dict_2[sb_top_select[2]], top_out_dict_3[sb_top_select[3]]
]
bottom_out_golden = [
bottom_out_dict_0[sb_bottom_select[0]],
bottom_out_dict_1[sb_bottom_select[1]],
bottom_out_dict_2[sb_bottom_select[2]],
bottom_out_dict_3[sb_bottom_select[3]]
]
# get actual sb out in int
left_out_actual = dut.left_out.value.integer
right_out_actual = dut.right_out.value.integer
top_out_actual = dut.top_out.value.integer
bottom_out_actual = dut.bottom_out.value.integer
# compare golden out and actual out
assert left_out_actual == bin_list_to_int_little_endian(
left_out_golden), "left out expecting %d, getting %d" % (
bin_list_to_int_little_endian(left_out_golden), left_out_actual)
assert right_out_actual == bin_list_to_int_little_endian(
right_out_golden), "right out expecting %d, getting %d" % (
bin_list_to_int_little_endian(right_out_golden), right_out_actual)
assert top_out_actual == bin_list_to_int_little_endian(
top_out_golden), "top out expecting %d, getting %d" % (
bin_list_to_int_little_endian(top_out_golden), top_out_actual)
assert bottom_out_actual == bin_list_to_int_little_endian(
bottom_out_golden), "bottom out expecting %d, getting %d" % (
bin_list_to_int_little_endian(bottom_out_golden),
bottom_out_actual)
# diectionary for finding golden cb out
# cb_<cb inst id>_dict_<bit id>
cb_0_dict_0 = {
0: left_out_golden[0],
1: left_in[0],
2: left_out_golden[2],
3: left_in[2]
}
cb_0_dict_1 = {
0: left_out_golden[1],
1: left_in[1],
2: left_out_golden[3],
3: left_in[3]
}
cb_1_dict_0 = {
0: bottom_in[0],
1: bottom_out_golden[0],
2: bottom_in[2],
3: bottom_out_golden[2]
}
cb_1_dict_1 = {
0: bottom_in[1],
1: bottom_out_golden[1],
2: bottom_in[3],
3: bottom_out_golden[3]
}
# cb golden out
cb_0_golden = [cb_0_dict_0[cb_0_config[0]], cb_0_dict_1[cb_0_config[1]]]
cb_1_golden = [cb_1_dict_0[cb_1_config[0]], cb_1_dict_1[cb_1_config[1]]]
# cb_0_0 to clb_in[2] in the tile above
assert dut.top_cb_out.value == cb_0_golden[
0], "cb_0_0 expecting %d, getting %d" % (cb_0_golden[0],
dut.top_cb_out.value)
# cb_0_1 to clb_in[0] in this tile
assert clb_in_actual[0] == cb_0_golden[
1], "cb_0_1 expecting %d, getting %d" % (cb_0_golden[1],
clb_in_actual[0])
# cb_1_0 to clb_in[1] in this tile
assert clb_in_actual[1] == cb_1_golden[
0], "cb_1_0 expecting %d, getting %d" % (cb_1_golden[0],
clb_in_actual[1])
# cb_1_1 to clb_in[3] in the tile to the right
assert dut.right_cb_out == cb_1_golden[
1], "cb_1_1 expecting %d, getting %d" % (cb_1_golden[1],
dut.right_cb_out)
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1,
dut.qsfp0_rx_clk_1,
dut.qsfp0_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start())
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1,
dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start())
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2,
dut.qsfp0_rx_clk_2,
dut.qsfp0_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start())
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2,
dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start())
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3,
dut.qsfp0_rx_clk_3,
dut.qsfp0_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start())
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3,
dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start())
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4,
dut.qsfp0_rx_clk_4,
dut.qsfp0_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start())
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4,
dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start())
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1,
dut.qsfp1_rx_clk_1,
dut.qsfp1_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start())
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1,
dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start())
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2,
dut.qsfp1_rx_clk_2,
dut.qsfp1_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start())
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2,
dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start())
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3,
dut.qsfp1_rx_clk_3,
dut.qsfp1_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start())
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3,
dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start())
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4,
dut.qsfp1_rx_clk_4,
dut.qsfp1_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4,
dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
def run_test(dut,
data_in=None,
config_coroutine=None,
idle_inserter=None,
backpressure_inserter=None):
cocotb.fork(Clock(dut.clock, 50, units='ns').start())
cocotb.fork(Clock(dut.s_axi_aclk, 11, units='ns').start())
tb = BasebandTB(dut) #, debug=True)
print("RESET STARTING")
yield tb.reset()
print("RESET DONE")
# yield tb.stream_in.send(b'0000000000000000')
# Start off optional coroutines
if config_coroutine is not None:
cocotb.fork(config_coroutine(tb))
if idle_inserter is not None:
tb.stream_in.set_valid_generator(idle_inserter())
if backpressure_inserter is not None:
tb.backpressure.start(backpressure_inserter())
print("COROUTINES STARTED")
# Wait 5 cycles before starting test
for i in range(5):
yield RisingEdge(dut.s_axi_aclk)
yield tb.set_timerx()
# yield tb.set_schedule(length=128, time=128)
yield tb.set_input_stream_mux()
yield tb.set_input_splitter_mux()
yield tb.set_aligner()
cocotb.fork(tb.append_channel())
cocotb.fork(tb.get_channel())
# get tx packet
print("STARTING MM -> TX")
# yield tb.transmit([0] * 20)
cocotb.fork(tb.transmit_forever([0] * 20))
cocotb.fork(tb.handle_packet_detect())
print("STARTING RX -> MM")
rx = cocotb.fork(tb.dma_to_mm(base=1024 * 4, size=128 // 4 - 1))
timeout = yield ClockCycles(dut.clock, 2000)
# wait
yield First(rx, timeout)
# print(len(tb.eq_monitor_in))
# print(tb.eq_monitor_in[0])
# plt.plot(range(len(tb.eq_monitor_in)), [i["bits_14_real"] for i in tb.eq_monitor_in])
# plt.show()
# expected_out = tb.fft_mon.expected_output()
# actual_out = tb.fft_mon.actual_output()
# plt.plot(expected_out.real)
# plt.plot(actual_out.real)
# plt.show()
# for i in range(len(tb.eq_monitor_in)):
# print(tb.eq_monitor_in[i])
raise tb.scoreboard.result
def setup_function(dut, key, plaintext):
cocotb.fork(Clock(dut.clk, CLK_PERIOD).start())
dut.rst = 0
dut.key = key
dut.block_i = plaintext
dut.enc_dec = 0
async def test_conv1d(dut):
""" Test Conv1D Module """
# Create a 10us period clock on port clk
clock = Clock(dut.clk_i, 10, units="us")
cocotb.fork(clock.start())
# Reset DUT
await FallingEdge(dut.clk_i)
dut.rst_n_i <= 0
dut.data_i <= 0
dut.valid_i <= 0
dut.last_i <= 0
dut.ready_i <= 0
dut.wr_en_i <= 0
dut.rd_en_i <= 0
dut.rd_wr_bank_i <= 0
dut.rd_wr_addr_i <= 0
dut.wr_data_i <= 0
await FallingEdge(dut.clk_i)
dut.rst_n_i <= 1
dut.ready_i <= 1
for _ in range(20):
await FallingEdge(dut.clk_i)
print('=' * 100)
print('Beginning basic test with fixed weights, biases, and features.')
print('=' * 100)
# w is weights, b is biases, s is shift, i is input features, o is expected
w = np.ones((3, 13, 8), dtype=np.int8) * 127
b = np.ones(8, dtype=np.int32)
s = 8
i = np.ones((50, 13), dtype=np.int8)
o = na.conv1d_multi_kernel(i, w, b)
o = na.scale_feature_map(o, s)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
print('=' * 100)
print(
'Beginning second basic test with fixed weights, biases, and features.'
)
print('=' * 100)
w = np.ones((3, 13, 8), dtype=np.int8) * 100
b = np.ones(8, dtype=np.int32)
s = 8
i = np.ones((50, 13), dtype=np.int8) * 2
o = na.conv1d_multi_kernel(i, w, b)
o = na.scale_feature_map(o, s)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
print('=' * 100)
print(
'Beginning third test with fixed weights and features, but varied biases.'
)
print('=' * 100)
w = np.ones((3, 13, 8), dtype=np.int8) * 50
b = np.arange(8, dtype=np.int32) * 2000 + 5
s = 8
i = np.ones((50, 13), dtype=np.int8)
o = na.conv1d_multi_kernel(i, w, b)
o = na.scale_feature_map(o, s)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
print('=' * 100)
print('Beginning test with random weights and features.')
print('=' * 100)
w, b, s, i, o = get_random_test_values(50, 13, 8, zero_biases=True)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
print('=' * 100)
print(
'Beginning saturation test with random weights, biases, and features.')
print('=' * 100)
w, b, s, i, o = get_random_test_values(50, 13, 8)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
# Now test with real weights, biases and MFCC features
total_samples = na.get_num_train_samples()
for test_num in range(10):
print('=' * 100)
print(
'Beginning conv1 test {}/{} with real weights, biases and features.'
.format(test_num, 10))
print('=' * 100)
w = na.conv1_weights
b = na.conv1_biases
s = na.bitshifts[0]
i = na.get_featuremap(np.random.randint(total_samples))
o = na.conv1d_multi_kernel(i, w, b)
o = na.scale_feature_map(o, s)
await write_conv_mem(dut, w, b, s)
await write_input_features(dut, i)
await read_output_features(dut, 50, 8, o)
async def init_test(dut):
cocotb.fork(Clock(dut.clk, 10, 'ns').start())
dut.rst <= 1
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
dut.rst <= 0
def setup_dut(dut):
cocotb.fork(Clock(dut.CLK, CLK_PERIOD).start())
def setup_clk(dut):
cocotb.fork(Clock(dut.clk, CLK_PERIOD, 'ns').start())
async def start(self, n):
c = Clock(self.dut.clk, self.period, self.unit)
clk_fork = cocotb.fork(c.start())
await Timer(n, "NS")
clk_fork.kill()
def test_ext_call_nreturn(dut):
"""Test ability to yield on an external non cocotb coroutine decorated
function"""
mon = cocotb.scheduler.queue(clock_monitor(dut))
clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
yield external(test_ext_function)(dut)
def setup_function(dut, key):
cocotb.fork(Clock(dut.clk, CLK_PERIOD).start())
dut.rst = 0
dut.key = key
dut.key_index = 0
def test_external_from_readonly(dut):
clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
yield ReadOnly()
dut._log.info("In readonly")
value = yield external(test_ext_function)(dut)
def test_direct_signal_indexing(dut):
"""Test directly accessing signal/net data in arrays, i.e. not iterating"""
tlog = logging.getLogger("cocotb.test")
cocotb.fork(Clock(dut.clk, 1000).start())
dut.port_desc_in <= 0
dut.port_asc_in <= 0
dut.port_ofst_in <= 0
yield Timer(2000)
dut.port_desc_in[2] <= 1
dut.port_asc_in[2] <= 1
dut.port_ofst_in[2] <= 1
yield Timer(2000)
tlog.info("Checking bit mapping from input to generate loops.")
if int(dut.desc_gen[2].sig) != 1:
raise TestFailure("Expected {0!r} to be a 1 but got {1}".format(
dut.desc_gen[2].sig, int(dut.desc_gen[2].sig)))
else:
tlog.info(" %r = %d", dut.desc_gen[2].sig, int(dut.desc_gen[2].sig))
if int(dut.asc_gen[18].sig) != 1:
raise TestFailure("Expected {0!r} to be a 1 but got {1}".format(
dut.asc_gen[18].sig, int(dut.asc_gen[18].sig)))
else:
tlog.info(" %r = %d", dut.asc_gen[18].sig, int(dut.asc_gen[18].sig))
tlog.info("Checking indexing of data with offset index.")
if int(dut.port_ofst_out) != 64:
raise TestFailure("Expected {0!r} to be a 64 but got {0}".format(
dut.port_ofst_out, int(dut.port_ofst_out)))
else:
tlog.info(" %r = %d (%s)", dut.port_ofst_out, int(dut.port_ofst_out),
dut.port_ofst_out.value.binstr)
tlog.info("Checking Types of complex array structures in signals.")
_check_type(tlog, dut.sig_desc[20], ModifiableObject)
_check_type(tlog, dut.sig_asc[17], ModifiableObject)
_check_type(tlog, dut.sig_t1, ModifiableObject)
_check_type(tlog, dut.sig_t2, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t2[5], ModifiableObject)
_check_type(tlog, dut.sig_t2[5][3], ModifiableObject)
_check_type(tlog, dut.sig_t3a[2][3], ModifiableObject)
_check_type(tlog, dut.sig_t3b[3], ModifiableObject)
_check_type(tlog, dut.sig_t3a, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t4, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t4[3], NonHierarchyIndexableObject)
# the following version cannot index into those arrays and will error out
if not (cocotb.LANGUAGE in ["verilog"]
and cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(
("2016.06", "2016.10", "2017.02"))):
_check_type(tlog, dut.sig_t4[3][4], ModifiableObject)
_check_type(tlog, dut.sig_t4[3][4][1], ModifiableObject)
_check_type(tlog, dut.sig_t5, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t5[1], NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t5[1][0], ModifiableObject)
_check_type(tlog, dut.sig_t5[1][0][6], ModifiableObject)
_check_type(tlog, dut.sig_t6, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t6[1], NonHierarchyIndexableObject)
# the following version cannot index into those arrays and will error out
if not (cocotb.LANGUAGE in ["verilog"]
and cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(
("2016.06", "2016.10", "2017.02"))):
_check_type(tlog, dut.sig_t6[0][3], ModifiableObject)
_check_type(tlog, dut.sig_t6[0][3][7], ModifiableObject)
_check_type(tlog, dut.sig_cmplx, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t7[1], NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t7[0][3], ModifiableObject)
_check_type(tlog, dut.sig_t8[1], NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_t8[0][3], ModifiableObject)
# Riviera has a bug and finds dut.sig_cmplx[1], but the type returned is a vpiBitVar
# only true for version 2016.02
if not (cocotb.LANGUAGE in ["verilog"]
and cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(("2016.02"))):
_check_type(tlog, dut.sig_cmplx[1], HierarchyObject)
_check_type(tlog, dut.sig_cmplx[1].a, ModifiableObject)
_check_type(tlog, dut.sig_cmplx[1].b, NonHierarchyIndexableObject)
_check_type(tlog, dut.sig_cmplx[1].b[1], ModifiableObject)
_check_type(tlog, dut.sig_cmplx[1].b[1][2], ModifiableObject)
_check_type(tlog, dut.sig_rec, HierarchyObject)
_check_type(tlog, dut.sig_rec.a, ModifiableObject)
_check_type(tlog, dut.sig_rec.b, NonHierarchyIndexableObject)
# Riviera has a bug and finds dut.sig_rec.b[1], but the type returned is 0 which is unknown
# only true for version 2016.02
if not (cocotb.LANGUAGE in ["verilog"]
and cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(("2016.02"))):
_check_type(tlog, dut.sig_rec.b[1], ModifiableObject)
_check_type(tlog, dut.sig_rec.b[1][2], ModifiableObject)
def setup_dut(dut):
cocotb.fork(Clock(dut.clock, CLOCK_PERIOD, units="ns").start())
def test_read_write(dut):
"""Test handle inheritance"""
tlog = logging.getLogger("cocotb.test")
cocotb.fork(Clock(dut.clk, 1000).start())
yield Timer(1000)
tlog.info("Checking Generics/Parameters:")
_check_logic(tlog, dut.param_logic, 1)
_check_logic(tlog, dut.param_logic_vec, 0xDA)
if cocotb.LANGUAGE in ["vhdl"]:
_check_int(tlog, dut.param_bool, 1)
_check_int(tlog, dut.param_int, 6)
_check_real(tlog, dut.param_real, 3.14)
_check_int(tlog, dut.param_char, ord('p'))
_check_str(tlog, dut.param_str, "ARRAYMOD")
if not cocotb.SIM_NAME.lower().startswith(("riviera")):
_check_logic(tlog, dut.param_rec.a, 0)
_check_logic(tlog, dut.param_rec.b[0], 0)
_check_logic(tlog, dut.param_rec.b[1], 0)
_check_logic(tlog, dut.param_rec.b[2], 0)
_check_logic(tlog, dut.param_cmplx[0].a, 0)
_check_logic(tlog, dut.param_cmplx[0].b[0], 0)
_check_logic(tlog, dut.param_cmplx[0].b[1], 0)
_check_logic(tlog, dut.param_cmplx[0].b[2], 0)
_check_logic(tlog, dut.param_cmplx[1].a, 0)
_check_logic(tlog, dut.param_cmplx[1].b[0], 0)
_check_logic(tlog, dut.param_cmplx[1].b[1], 0)
_check_logic(tlog, dut.param_cmplx[1].b[2], 0)
tlog.info("Checking Constants:")
_check_logic(tlog, dut.const_logic, 0)
_check_logic(tlog, dut.const_logic_vec, 0x3D)
if cocotb.LANGUAGE in ["vhdl"]:
_check_int(tlog, dut.const_bool, 0)
_check_int(tlog, dut.const_int, 12)
_check_real(tlog, dut.const_real, 6.28)
_check_int(tlog, dut.const_char, ord('c'))
_check_str(tlog, dut.const_str, "MODARRAY")
if not cocotb.SIM_NAME.lower().startswith(("riviera")):
_check_logic(tlog, dut.const_rec.a, 1)
_check_logic(tlog, dut.const_rec.b[0], 0xFF)
_check_logic(tlog, dut.const_rec.b[1], 0xFF)
_check_logic(tlog, dut.const_rec.b[2], 0xFF)
_check_logic(tlog, dut.const_cmplx[1].a, 1)
_check_logic(tlog, dut.const_cmplx[1].b[0], 0xFF)
_check_logic(tlog, dut.const_cmplx[1].b[1], 0xFF)
_check_logic(tlog, dut.const_cmplx[1].b[2], 0xFF)
_check_logic(tlog, dut.const_cmplx[2].a, 1)
_check_logic(tlog, dut.const_cmplx[2].b[0], 0xFF)
_check_logic(tlog, dut.const_cmplx[2].b[1], 0xFF)
_check_logic(tlog, dut.const_cmplx[2].b[2], 0xFF)
dut.select_in = 2
yield Timer(1000)
tlog.info("Writing the signals!!!")
dut.sig_logic = 1
dut.sig_logic_vec = 0xCC
if cocotb.LANGUAGE in ["vhdl"]:
dut.sig_bool = 1
dut.sig_int = 5000
dut.sig_real = 22.54
dut.sig_char = ord('Z')
dut.sig_str = "Testing"
dut.sig_rec.a = 1
dut.sig_rec.b[0] = 0x01
dut.sig_rec.b[1] = 0x23
dut.sig_rec.b[2] = 0x45
dut.sig_cmplx[0].a = 0
dut.sig_cmplx[0].b[0] = 0x67
dut.sig_cmplx[0].b[1] = 0x89
dut.sig_cmplx[0].b[2] = 0xAB
dut.sig_cmplx[1].a = 1
dut.sig_cmplx[1].b[0] = 0xCD
dut.sig_cmplx[1].b[1] = 0xEF
dut.sig_cmplx[1].b[2] = 0x55
yield Timer(1000)
tlog.info("Checking writes:")
_check_logic(tlog, dut.port_logic_out, 1)
_check_logic(tlog, dut.port_logic_vec_out, 0xCC)
if cocotb.LANGUAGE in ["vhdl"]:
_check_int(tlog, dut.port_bool_out, 1)
_check_int(tlog, dut.port_int_out, 5000)
_check_real(tlog, dut.port_real_out, 22.54)
_check_int(tlog, dut.port_char_out, ord('Z'))
_check_str(tlog, dut.port_str_out, "Testing")
_check_logic(tlog, dut.port_rec_out.a, 1)
_check_logic(tlog, dut.port_rec_out.b[0], 0x01)
_check_logic(tlog, dut.port_rec_out.b[1], 0x23)
_check_logic(tlog, dut.port_rec_out.b[2], 0x45)
_check_logic(tlog, dut.port_cmplx_out[0].a, 0)
_check_logic(tlog, dut.port_cmplx_out[0].b[0], 0x67)
_check_logic(tlog, dut.port_cmplx_out[0].b[1], 0x89)
_check_logic(tlog, dut.port_cmplx_out[0].b[2], 0xAB)
_check_logic(tlog, dut.port_cmplx_out[1].a, 1)
_check_logic(tlog, dut.port_cmplx_out[1].b[0], 0xCD)
_check_logic(tlog, dut.port_cmplx_out[1].b[1], 0xEF)
_check_logic(tlog, dut.port_cmplx_out[1].b[2], 0x55)
tlog.info("Writing a few signal sub-indices!!!")
dut.sig_logic_vec[2] = 0
if cocotb.LANGUAGE in ["vhdl"] or not (cocotb.SIM_NAME.lower().startswith(
("ncsim")) or (cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(
("2016.06", "2016.10", "2017.02")))):
dut.sig_t6[1][3][2] = 1
dut.sig_t6[0][2][7] = 0
if cocotb.LANGUAGE in ["vhdl"]:
dut.sig_str[2] = ord('E')
dut.sig_rec.b[1][7] = 1
dut.sig_cmplx[1].b[1][0] = 0
yield Timer(1000)
tlog.info("Checking writes (2):")
_check_logic(tlog, dut.port_logic_vec_out, 0xC8)
if cocotb.LANGUAGE in ["vhdl"] or not (cocotb.SIM_NAME.lower().startswith(
("ncsim")) or (cocotb.SIM_NAME.lower().startswith(
("riviera")) and cocotb.SIM_VERSION.startswith(
("2016.06", "2016.10", "2017.02")))):
_check_logic(tlog, dut.sig_t6[1][3][2], 1)
_check_logic(tlog, dut.sig_t6[0][2][7], 0)
if cocotb.LANGUAGE in ["vhdl"]:
_check_str(tlog, dut.port_str_out, "TEsting")
_check_logic(tlog, dut.port_rec_out.b[1], 0xA3)
_check_logic(tlog, dut.port_cmplx_out[1].b[1], 0xEE)
def create_clock(dut):
cocotb.fork(Clock(dut.clk, 10, 'ns').start())
def setup_function(dut, salt, count, user_password):
cocotb.fork(Clock(dut.clk, CLK_PERIOD).start())
dut.rst = 0
dut.salt = salt
dut.count = count
dut.user_password = user_password
def simple_reads(dut):
"""Test simple sequence of reads"""
# Start clock
cocotb.fork(Clock(dut.clk, 5000).start())
# Reset cache
dut.reset = 1
dut.addr = 0
dut.data_in = 0
dut.mem_read = 0
dut.mem_write = 0
dut.mem_type = 1 # Word
dut.mem_write_ack = 0
dut.mem_read_ack = 0
dut.mem_read_data = 0
yield FallingEdge(dut.clk)
# Unset reset
dut.reset = 0
# At this point the cache should have only invalid lines
# Try this by reading from an address => expect hit = 0
dut.mem_read = 1
dut.addr = 0x00000104
yield Timer(10)
# Hit is immediate
if int(dut.hit) != 0:
raise TestFailure("Cache should be empty, but we have a hit")
yield FallingEdge(dut.clk)
# Now the request will be issued
if int(dut.mem_read_req) != 1:
raise TestFailure("The cache should have issued a memory read request")
if int(dut.mem_read_addr) != 0x00000100:
raise TestFailure("Wrong read address: 0x%08x, expected: 0x00000100" % int(dut.mem_read_addr))
# To simulate the memory we send the data
# The size of a cache line is 128 bits => 16 Bytes
dut.mem_read_data = 0xf0e0d0c0b0a090807060504030201000
dut.mem_read_ack = 1
yield FallingEdge(dut.clk)
dut.mem_read_ack = 0
# Now we should be able to read successfully
# We select the second word => 0x70605040
if int(dut.hit) != 1:
raise TestFailure("We expect a hit")
if int(dut.data_out) != 0x70605040:
raise TestFailure("Wrong data out: 0x%08x, expected: 0x70605040" % int(dut.data_out))
yield FallingEdge(dut.clk)
# Change address offset
dut.addr = 0x00000100
yield Timer(10)
if int(dut.hit) != 1:
raise TestFailure("We expect a hit")
if int(dut.data_out) != 0x30201000:
raise TestFailure("Wrong data out: 0x%08x, expected: 0x30201000" % int(dut.data_out))
# Change address tag
dut.addr = 0x00000200
yield Timer(10)
if int(dut.hit) != 0:
raise TestFailure("We expect a miss (different tags)")
def setup_dut(dut):
cocotb.fork(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())