async def test_force_release(dut):
"""
Test force and release on simulation handles
"""
log = logging.getLogger("cocotb.test")
await Timer(10, "ns")
dut.stream_in_data <= 4
dut.stream_out_data_comb <= Force(5)
await Timer(10, "ns")
got_in = int(dut.stream_in_data)
got_out = int(dut.stream_out_data_comb)
log.info("dut.stream_in_data = %d" % got_in)
log.info("dut.stream_out_data_comb = %d" % got_out)
if got_in == got_out:
raise TestFailure(
"stream_in_data and stream_out_data_comb should not match when force is active!"
)
dut.stream_out_data_comb <= Release()
dut.stream_in_data <= 3
await Timer(10, "ns")
got_in = int(dut.stream_in_data)
got_out = int(dut.stream_out_data_comb)
log.info("dut.stream_in_data = %d" % got_in)
log.info("dut.stream_out_data_comb = %d" % got_out)
if got_in != got_out:
raise TestFailure(
"stream_in_data and stream_out_data_comb should match when output was released!"
)
async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
TotalBitsCount = 0
PreviousSync = 0
# Locking Signal
with open(BitFile, "r") as fp:
dut._log.info(f"Bitfile opened {BitFile}")
syncPts = math.ceil(BitstreamLen/4800)
InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
for inst, eachModule in ccPaths.items():
BitsCount = 0
for eachPath in eachModule:
size = eachPath["width"]
BitsCount += size
try:
Stream = fp.read(size)
bits = int(Stream, 2)
except:
dut._log.info(f"Padding Zero")
bits = 0
eachPath["obj"] <= Force(bits)
TotalBitsCount += BitsCount
dut._log.info(f"Configured {inst} with {BitsCount} bits ")
dut.ccff_head_pad <= InitialBits.pop()
await FallingEdge(dut.prog_clk_pad)
# Releasing Signals
PreviousSync = 0
TotalBitsCount = 0
for inst, eachModule in ccPaths.items():
for eachPath in eachModule:
eachPath["obj"] <= Release()
TotalBitsCount += eachPath["width"]
if (TotalBitsCount-PreviousSync) > 4800:
dut.ccff_head_pad <= InitialBits.pop()
await FallingEdge(dut.prog_clk_pad)
PreviousSync = TotalBitsCount
dut._log.info(f"Releasing config of {inst}")
dut.ccff_head_pad <= InitialBits.pop()
await FallingEdge(dut.prog_clk_pad)
dut._log.info(f"Configured {TotalBitsCount} bits")
async def test_force_release(dut):
"""
Test force and release on simulation handles
"""
log = logging.getLogger("cocotb.test")
await Timer(10, "ns")
dut.stream_in_data <= 4
dut.stream_out_data_comb <= Force(5)
await Timer(10, "ns")
got_in = int(dut.stream_in_data)
got_out = int(dut.stream_out_data_comb)
log.info("dut.stream_in_data = %d" % got_in)
log.info("dut.stream_out_data_comb = %d" % got_out)
assert got_in != got_out
dut.stream_out_data_comb <= Release()
dut.stream_in_data <= 3
await Timer(10, "ns")
got_in = int(dut.stream_in_data)
got_out = int(dut.stream_out_data_comb)
log.info("dut.stream_in_data = %d" % got_in)
log.info("dut.stream_out_data_comb = %d" % got_out)
assert got_in == got_out