def test_context():
context = coreir.Context()
_type = context.named_types[("coreir", "clkIn")]
assert _type.kind == "Named"
def load_src(src_filename, context: coreir.Context = None):
if context is None:
context = coreir.Context()
context.load_library("commonlib")
return context.load_from_file(src_filename)
def test_save_module():
c = coreir.Context()
module_typ = c.Record({
"input": c.Array(8, c.BitIn()),
"output": c.Array(9, c.Bit())
})
module = c.global_namespace.new_module("multiply_by_2", module_typ)
module.print_()
assert module.definition is None, "Should not have a definition"
module_def = module.new_definition()
configparams = c.newParams({
"init": c.Int(),
"test_param0": c.Int(),
"test_param1": c.Int()
})
add8 = c.global_namespace.new_module(
"add8",
c.Record({
"in1": c.Array(8, c.BitIn()),
"in2": c.Array(8, c.BitIn()),
"out": c.Array(9, c.Bit())
}), configparams)
for port, type_ in add8.type.items():
assert type_.kind == "Array"
if port in ["in1", "in2"]:
assert len(type_) == 8
else:
assert len(type_) == 9
add8_inst = module_def.add_module_instance(
"adder", add8,
c.new_values({
"init": 5,
"test_param0": 1,
"test_param1": 0
}))
assert add8_inst.module.namespace.name == "global"
assert add8_inst.module.name == "add8"
assert add8_inst.config["init"].value == 5
expected = {"init": 5, "test_param0": 1, "test_param1": 0}
assert len(add8_inst.config) == len(expected)
for key, value in add8_inst.config.items():
assert key in expected and expected[key] == value.value
del expected[key]
assert not expected, "Should be empty"
add8_in1 = add8_inst.select("in1")
add8_in2 = add8_inst.select("in2")
add8_out = add8_inst.select("out")
interface = module_def.interface
_input = interface.select("input")
output = interface.select("output")
try:
interface.select("BadSelect")
assert (False)
except Exception:
pass
module_def.connect(_input, add8_in1)
module_def.connect(_input, add8_in2)
module_def.connect(output, add8_out)
module.definition = module_def
assert module.definition is not None, "Should have a definition"
module.print_()
module.save_to_file("_python_test_output.json")
mod = c.load_from_file("_python_test_output.json")
mod_def = mod.definition
print("=====================")
mod_def.print_()
module_def.print_()
print("=====================")
c.run_passes(['printer'])
def reset_instance(self):
self.__instance = coreir.Context()
def __init__(self):
self.__instance = coreir.Context()
from magma import *
import coreir
context = coreir.Context()
def get_lib(lib):
if lib in {"coreir", "mantle", "corebit"}:
return context.get_namespace(lib)
elif lib == "global":
return context.global_namespace
else:
return context.load_library(lib)
def import_generator(lib, name):
generator = get_lib(lib).generators[name]
def _generator(**kwargs):
return import_circuit(generator(**kwargs))
return _generator
def to_magma_type(typ):
if typ.kind == "Array":
return Array(len(typ), to_magma_type(typ.element_type))
elif typ.kind == "BitIn":
return In(Bit)
elif typ.kind == "Bit":
return Out(Bit)
from mantle.primitives import DeclareAdd from mac import MAC # convolution window size x = 3 y = 3 # image size (height and width) im_w = 16 im_h = 16 width = 1 TIN = m.Array(width, m.BitIn) TOUT = m.Array(width, m.Out(m.Bit)) c = coreir.Context() cirb = CoreIRBackend(c) # Line Buffer interface in_LB = m.Array(1, m.Array(1, TIN)) # one image row per clock out_LB = m.Array(y, m.Array(x, TOUT)) # convolution window imgType = m.Array(im_h, m.Array(im_w, TIN)) # image dimensions # multiply-accumulate interface in_MAC = m.Array(x * y, m.BitIn) out_MAC = m.Out(m.Bit) # weight input interface in_W = m.Array(y, m.Array(x, TIN)) # Top level module: line buffer input, MAC output
def check_graph_isomorphic(graphs: Dict[int, InterconnectGraph],
filename: str):
assert os.path.isfile(filename)
context = coreir.Context()
context.load_library('commonlib')
mod = context.load_from_file(filename)
tile_modules = {}
for instance in mod.definition.instances:
assert instance.name == instance.selectpath[0]
if instance.name[:4] == "Tile":
tile_modules[instance.name] = instance.module
# checked pairs from graph
# because there are many connections un-related to the inter-connect
# we hold account for every connection checked in the cyclone based ont he
# RTL
checked_node_connection: Set[Tuple[Node, Node]] = set()
# CHECK 1:
# we verify inter-tile connections first. making sure it's bijective
tile_connections: List[Tuple[List[str], List[str]]] = []
for conn in mod.directed_module.connections:
src: List[str] = conn.source
dst: List[str] = conn.sink
src_name: str = src[0]
dst_name: str = dst[0]
src_node_name: str = src[1]
dst_node_name: str = dst[1]
if src_name[:4].lower() == "tile" and dst_name[:4].lower() == "tile" \
and src_node_name[:2] == "SB" and dst_node_name[:2] == "SB":
tile_connections.append((src, dst))
# verify RTL -> cyclone
for src, dst in tile_connections:
src_node = get_node_from_tile(graphs, src)
dst_node = get_node_from_tile(graphs, dst)
assert src_node is not None, "ERROR in hardware creation"
assert dst_node is not None, "ERROR in hardware creation"
verify_inter_tile_connection_rtl(src_node, dst_node,
checked_node_connection)
# verify cyclone -> RTL
for _, graph in graphs.items():
for x, y in graph:
tile: Tile = graph.get_tile(x, y)
sb_nodes = tile.switchbox.get_all_sbs()
verify_inter_tile_connection_cyclone(sb_nodes, tile_connections)
# CHECK 2
# this is not part of the graph isomorphism check, yet it's very
# important that ports lifted to the tile level are actually connected
for tile_name, tile_module in tile_modules.items():
verify_tile_lift_connection(graphs, tile_module, tile_name)
# CHECK 3
# after verifying the inter-tile connections, we need to check if the
# switch box is created correctly. This will cover pipeline register check
# verify RTL -> cyclone
for tile_name, tile_module in tile_modules.items():
verify_sb_rtl(graphs, tile_module, tile_name, checked_node_connection)
# verify cyclone -> RTL
for _, graph in graphs.items():
for x, y in graph:
tile: Tile = graph.get_tile(x, y)
switchbox = tile.switchbox
verify_sb_cyclone(switchbox, tile_modules)
# CHECK 4:
# This is to check if the port connection is correct, this means to check
# port <-> CB/SB in both internal module and module connection
# (due to port lifting)
# verify RTL -> cyclone
for tile_name, tile_module in tile_modules.items():
verify_port_rtl(graphs, tile_module, tile_name,
checked_node_connection)
# verify cyclone -> RTL
for _, graph in graphs.items():
for x, y in graph:
tile = graph.get_tile(x, y)
verify_port_cyclone(tile, tile_modules)
def test_type_size():
context = coreir.Context()
array1_type = context.Array(7, context.BitIn())
assert array1_type.size == 7
array2_type = context.Array(10, array1_type)
assert array2_type.size == 7 * 10
def test_type_isoutput():
context = coreir.Context()
array1_type = context.Array(7, context.Bit())
assert array1_type.is_output()
assert not array1_type.is_input()