def gen_add_input2(
dfg: AGraph, fu: AGraph,
input_map: Dict[str, int]) -> Tuple[List[Input], List[Output]]:
outputs: List[Output] = []
inputs: List[Input] = []
nodes: List[Instruction] = []
for node in fu.nodes():
nodes.append(parse_instruction(node))
nodes.sort()
prev_o = 0
for node in nodes:
preds = dfg.predecessors(node.name)
parent0 = parse_instruction(preds[0])
parent1 = parse_instruction(preds[1])
if parent0.name in input_map:
label = dfg.get_node(parent0.name).attr['label']
if 'mul' in label:
latency = 2
else:
latency = 1
i0 = prev_o + 1
inputs.append(
Input(i0, input_map[parent0.name], parent0.cycle + latency))
else:
for output in outputs:
if output.cycle == parent0.cycle + 1:
i0 = output.val
break
if parent1.name in input_map:
label = dfg.get_node(parent1.name).attr['label']
if 'mul' in label:
latency = 2
else:
latency = 1
i1 = prev_o + 1
inputs.append(
Input(i1, input_map[parent1.name], parent1.cycle + latency))
else:
for output in outputs:
if output.cycle == parent1.cycle + 1:
i1 = output.val
break
expected = i0 + i1
prev_o = expected
outputs.append(Output(expected, node.cycle + 1))
inputs.sort()
return inputs, outputs
def gen_alloc_insts(rf_allocs: List[RFallocation], dfg: AGraph, fu: AGraph,
input_map: Dict[str, int]) -> List[ATAI]:
rf_insts = []
for rf_alloc in rf_allocs:
inst = parse_instruction(dfg.get_node(rf_alloc.name))
if rf_alloc.type == RFallocation.FUTypes.MUL:
latency = Config.MUL_LATENCY
elif rf_alloc.type == RFallocation.FUTypes.ADD:
latency = Config.ADD_LATENCY
else:
# TODO: load inst latency?
latency = 1
if rf_alloc.name in fu:
input_type = OpInput()
else:
# TODO: map fu input
input_type = FUinput(input_map[rf_alloc.name])
if input_type is None:
raise AllocException('alloc not found in input map')
cycle = inst.cycle + latency
rf_insts.append(ATAStore(input_type, rf_alloc.address, cycle))
return rf_insts
def gen_op_insts(rf_allocs: List[RFallocation], dfg: AGraph, fu: AGraph,
input_map: Dict[str, int]) -> List[ATAI]:
assembly = []
instructions: List[Instruction] = []
for instruction in fu.nodes():
instructions.append(parse_instruction(instruction))
for instruction in instructions:
n = dfg.get_node(instruction.name)
nodes = dfg.predecessors(n)
input_type0 = inst_input_type(rf_allocs, fu, nodes[0])
if len(nodes) > 1:
input_type1 = inst_input_type(rf_allocs, fu, nodes[1])
else:
input_type1 = input_type0
# This should never occur but we check for it anyways
if input_type0 == OpInput and input_type1 == OpInput:
if nodes[0] != nodes[1]:
raise DoubleUnidenticalOPInputException
# TODO: find scheduling for fetch ops might need to be swapped to fit?
if input_type0 == RFInput:
# If the data is in the RF we need to generate fetch instructions
assembly.append(
generate_fetch(rf_allocs, instruction, nodes[0],
ATAFetch.REG.REG0))
input0 = RFInput()
elif input_type0 == OpInput:
input0 = OpInput()
else:
n = input_map[nodes[0].get_name()]
if n is None:
raise FUinputException(
'Cannot find FU from which predecessing node originates in map'
)
input0 = FUinput(n)
if input_type1 == RFInput:
assembly.append(
generate_fetch(rf_allocs, instruction, nodes[1],
ATAFetch.REG.REG1))
input1 = RFInput()
elif input_type1 == OpInput:
input1 = OpInput()
else:
n = input_map[nodes[1].get_name()]
if n is None:
raise FUinputException(
'Cannot find FU from which predecessing node originates in map'
)
input1 = FUinput(n)
assembly.append(ATAOp(input0, input1, instruction.cycle))
return assembly
def gen_mul_inputs(
dfg: AGraph, fu: AGraph,
input_map: Dict[str, int]) -> Tuple[List[Input], List[Output]]:
outputs: List[Output] = []
inputs: List[Input] = []
nodes: List[Instruction] = []
for node in fu.nodes():
nodes.append(parse_instruction(node))
nodes.sort()
prime_idx = 0
for node in nodes:
preds = dfg.predecessors(node.name)
parent0 = parse_instruction(preds[0])
parent1 = parse_instruction(preds[1])
label0 = dfg.get_node(parent0.name).attr['label']
label1 = dfg.get_node(parent1.name).attr['label']
i0, edge_case0, prime_idx = gen_mul_input(node, parent0, input_map,
inputs, outputs, prime_idx,
label0)
i1, edge_case1, prime_idx = gen_mul_input(node, parent1, input_map,
inputs, outputs, prime_idx,
label1)
if edge_case0 or edge_case1:
expected = None
else:
expected = i0 * i1
# if parent0.name in input_map:
# label = dfg.get_node(parent0.name).attr['label']
# if 'mul' in label:
# latency = 2
# else:
# latency = 1
#
# i0 = PRIMES[prime_idx]
# prime_idx += 1
# inputs.append(Input(i0, input_map[parent0.name], parent0.cycle + latency))
# else:
# for output in outputs:
# if output.cycle == parent0.cycle + 2:
# i0 = output.val
# break
#
# if parent1.name in input_map:
# label = dfg.get_node(parent1.name).attr['label']
# if 'mul' in label:
# latency = 2
# else:
# latency = 1
#
# i1 = PRIMES[prime_idx]
# prime_idx += 1
# inputs.append(Input(i1, input_map[parent1.name], parent1.cycle + latency))
# else:
# for output in outputs:
# if output.cycle == parent1.cycle + 2:
# i1 = output.val
# break
# expected = i0 * i1
outputs.append(Output(expected, node.cycle + 1))
inputs.sort()
return inputs, outputs