def print_time(name, now_time, last_time=None, indentation=2): """ Print a statement about the time delta. """ global OPTS # Don't print during testing if not OPTS.is_unit_test or OPTS.debug_level>0: if last_time: time = str(round((now_time-last_time).total_seconds(),1)) + " seconds" else: time = now_time.strftime('%m/%d/%Y %H:%M:%S') debug.print_raw("{0} {1}: {2}".format("*"*indentation,name,time))
def save(self): """ Save all the output files while reporting time to do it as well. """ # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) functional(self.s, os.path.basename(spname), cycles=200, output_path=OPTS.output_path) print_time("Spice writing", datetime.datetime.now(), start_time) if not OPTS.netlist_only: # Write the layout start_time = datetime.datetime.now() gdsname = OPTS.output_path + self.s.name + ".gds" debug.print_raw("GDS: Writing to {0}".format(gdsname)) self.gds_write(gdsname) if OPTS.check_lvsdrc: verify.write_drc_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), extract=True, final_verification=True, output_path=OPTS.output_path) print_time("GDS", datetime.datetime.now(), start_time) # Create a LEF physical model start_time = datetime.datetime.now() lefname = OPTS.output_path + self.s.name + ".lef" debug.print_raw("LEF: Writing to {0}".format(lefname)) self.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) # Save the LVS file start_time = datetime.datetime.now() lvsname = OPTS.output_path + self.s.name + ".lvs.sp" debug.print_raw("LVS: Writing to {0}".format(lvsname)) self.lvs_write(lvsname) if not OPTS.netlist_only and OPTS.check_lvsdrc: verify.write_lvs_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), sp_name=os.path.basename(lvsname), final_verification=True, output_path=OPTS.output_path) print_time("LVS writing", datetime.datetime.now(), start_time) # Save the extracted spice file if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) sp_file = pexname print_time("Extraction", datetime.datetime.now(), start_time) else: # Use generated spice file for characterization sp_file = spname # Save a functional simulation file # Characterize the design start_time = datetime.datetime.now() from characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) # Write the config file start_time = datetime.datetime.now() from shutil import copyfile copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw( "Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time) # Write out options if specified if OPTS.output_extended_config: start_time = datetime.datetime.now() oname = OPTS.output_path + OPTS.output_name + "_extended.py" debug.print_raw("Extended Config: Writing to {0}".format(oname)) self.extended_config_write(oname) print_time("Extended Config", datetime.datetime.now(), start_time)
def report_status(): """ Check for valid arguments and report the info about the SRAM being generated """ global OPTS # Check if all arguments are integers for bits, size, banks if type(OPTS.word_size) != int: debug.error("{0} is not an integer in config file.".format( OPTS.word_size)) if type(OPTS.num_words) != int: debug.error("{0} is not an integer in config file.".format( OPTS.sram_size)) if type(OPTS.write_size) is not int and OPTS.write_size is not None: debug.error("{0} is not an integer in config file.".format( OPTS.write_size)) # If a write mask is specified by the user, the mask write size should be the same as # the word size so that an entire word is written at once. if OPTS.write_size is not None: if (OPTS.word_size % OPTS.write_size != 0): debug.error( "Write size needs to be an integer multiple of word size.") # If write size is more than half of the word size, # then it doesn't need a write mask. It would be writing # the whole word. if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size / 2): debug.error( "Write size needs to be between 1 bit and {0} bits/2.".format( OPTS.word_size)) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") debug.print_raw("Technology: {0}".format(OPTS.tech_name)) total_size = OPTS.word_size * OPTS.num_words * OPTS.num_banks debug.print_raw("Total size: {} bits".format(total_size)) if total_size >= 2**14: debug.warning( "Requesting such a large memory size ({0}) will have a large run-time. " .format(total_size) + "Consider using multiple smaller banks.") debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format( OPTS.word_size, OPTS.num_words, OPTS.num_banks)) if (OPTS.write_size != OPTS.word_size): debug.print_raw("Write size: {}".format(OPTS.write_size)) debug.print_raw( "RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format( OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports)) if OPTS.netlist_only: debug.print_raw( "Netlist only mode (no physical design is being done, netlist_only=False to disable)." ) if not OPTS.route_supplies: debug.print_raw( "Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing)." ) if not OPTS.inline_lvsdrc: debug.print_raw( "DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking)." ) if not OPTS.check_lvsdrc: debug.print_raw( "DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).") if OPTS.analytical_delay: debug.print_raw( "Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate)." ) else: if OPTS.spice_name != "": debug.print_raw( "Performing simulation-based characterization with {}".format( OPTS.spice_name)) if OPTS.trim_netlist: debug.print_raw( "Trimming netlist to speed up characterization (trim_netlist=False to disable)." ) if OPTS.nominal_corner_only: debug.print_raw("Only characterizing nominal corner.")
def print_banner(): """ Conditionally print the banner to stdout """ global OPTS if OPTS.is_unit_test: return debug.print_raw( "|==============================================================================|" ) debug.print_raw("|=========" + NAME.center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|") debug.print_raw("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|") debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|") debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|") user_info = "Usage help: [email protected]" debug.print_raw("|=========" + user_info.center(60) + "=========|") dev_info = "Development help: [email protected]" debug.print_raw("|=========" + dev_info.center(60) + "=========|") temp_info = "Temp dir: {}".format(OPTS.openram_temp) debug.print_raw("|=========" + temp_info.center(60) + "=========|") debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|") debug.print_raw( "|==============================================================================|" )
# Keep track of running stats start_time = datetime.datetime.now() g.print_time("Start", start_time) # Output info about this run g.report_status() from sram_config import sram_config # Configure the SRAM organization c = sram_config(word_size=OPTS.word_size, num_words=OPTS.num_words, write_size=OPTS.write_size) debug.print_raw("Words per row: {}".format(c.words_per_row)) output_extensions = ["sp", "v", "lib", "py", "html", "log"] # Only output lef/gds if back-end if not OPTS.netlist_only: output_extensions.extend(["lef", "gds"]) output_files = ["{0}{1}.{2}".format(OPTS.output_path, OPTS.output_name, x) for x in output_extensions] debug.print_raw("Output files are: ") for path in output_files: debug.print_raw(path) from sram import sram
def report_status(): """ Check for valid arguments and report the info about the SRAM being generated """ global OPTS # Check if all arguments are integers for bits, size, banks if type(OPTS.word_size) != int: debug.error("{0} is not an integer in config file.".format( OPTS.word_size)) if type(OPTS.num_words) != int: debug.error("{0} is not an integer in config file.".format( OPTS.sram_size)) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") debug.print_raw("Technology: {0}".format(OPTS.tech_name)) debug.print_raw("Total size: {} bits".format( OPTS.word_size * OPTS.num_words * OPTS.num_banks)) debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format( OPTS.word_size, OPTS.num_words, OPTS.num_banks)) debug.print_raw( "RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format( OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports)) if OPTS.netlist_only: debug.print_raw( "Netlist only mode (no physical design is being done).") if not OPTS.inline_lvsdrc: debug.print_raw("DRC/LVS/PEX is only run on the top-level design.") if not OPTS.check_lvsdrc: debug.print_raw("DRC/LVS/PEX is completely disabled.")
def save(self): """ Save all the output files while reporting time to do it as well. """ if not OPTS.netlist_only: # Create a LEF physical model start_time = datetime.datetime.now() lefname = OPTS.output_path + self.s.name + ".lef" debug.print_raw("LEF: Writing to {0}".format(lefname)) self.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) # Write the layout start_time = datetime.datetime.now() gdsname = OPTS.output_path + self.s.name + ".gds" debug.print_raw("GDS: Writing to {0}".format(gdsname)) self.gds_write(gdsname) print_time("GDS", datetime.datetime.now(), start_time) # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) print_time("Spice writing", datetime.datetime.now(), start_time) # Save the LVS file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".lvs" debug.print_raw("LVS: Writing to {0}".format(spname)) self.lvs_write(spname) print_time("LVS writing", datetime.datetime.now(), start_time) # Save the extracted spice file if OPTS.use_pex: import verify start_time = datetime.datetime.now() # Output the extracted design if requested sp_file = OPTS.output_path + "temp_pex.sp" verify.run_pex(self.s.name, gdsname, spname, output=sp_file) print_time("Extraction", datetime.datetime.now(), start_time) else: # Use generated spice file for characterization sp_file = spname # Characterize the design start_time = datetime.datetime.now() from characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) # Write the config file start_time = datetime.datetime.now() from shutil import copyfile copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw( "Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time)
def report_status(): """ Check for valid arguments and report the info about the SRAM being generated """ global OPTS # Check if all arguments are integers for bits, size, banks if type(OPTS.word_size) != int: debug.error("{0} is not an integer in config file.".format( OPTS.word_size)) if type(OPTS.num_words) != int: debug.error("{0} is not an integer in config file.".format( OPTS.sram_size)) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") debug.print_raw("Technology: {0}".format(OPTS.tech_name)) total_size = OPTS.word_size * OPTS.num_words * OPTS.num_banks debug.print_raw("Total size: {} bits".format(total_size)) if total_size >= 2**14: debug.warning( "Requesting such a large memory size ({0}) will have a large run-time. " .format(total_size) + "Consider using multiple smaller banks.") debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format( OPTS.word_size, OPTS.num_words, OPTS.num_banks)) debug.print_raw( "RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format( OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports)) if OPTS.netlist_only: debug.print_raw( "Netlist only mode (no physical design is being done, netlist_only=False to disable)." ) if not OPTS.route_supplies: debug.print_raw( "Design supply routing skipped for run-time (incomplete GDS will not be saved) (route_supplies=True to enable)." ) if not OPTS.inline_lvsdrc: debug.print_raw( "DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to enable)." ) if not OPTS.check_lvsdrc: debug.print_raw( "DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).") if OPTS.analytical_delay: debug.print_raw( "Characterization is disabled (using analytical delay models) (analytical_delay=False to enable)." ) else: if OPTS.spice_name != "": debug.print_raw( "Performing simulation-based characterization with {}".format( OPTS.spice_name)) if OPTS.trim_netlist: debug.print_raw( "Trimming netlist to speed up characterization (trim_netlist=False to disable)." )