Ejemplo n.º 1
0
 def _compile_program_file_t(self, file_content):
     """
     Running in its own thread, this method will compile the provided
     VHDL code and then program the board if the result is successful.
     """
     self._current_state = STATE_SYNTHESIZING
     c = Compiler(self._compiling_files_path, self._compiling_tools_path)
     #c.DEBUG = True
     content = base64.b64decode(file_content)
     c.feed_vhdl(content)
     if DEBUG: print "[DBG]: VHDL fed. Now compiling."
     success = c.compileit()
     if(not success):
         self._current_state = STATE_SYNTHESIZING_ERROR
         self._compiling_result = c.errors()
     else:
         # If we are using adaptive timing, modify it according to this last input.
         # TODO: Consider limiting the allowed range of variation, in order to dampen potential anomalies.
         elapsed = c.get_time_elapsed()
         if(self._adaptive_time):
             self._programmer_time = elapsed
         
         bitfile = c.retrieve_bitfile()
         if DEBUG: print "[DBG]: .BIT retrieved after successful compile. Now programming."
         c._compiling_result = "Synthesizing done."
         self._program_file_t(bitfile)
Ejemplo n.º 2
0
    def _compile_program_file_t(self, file_content):
        """
        Running in its own thread, this method will compile the provided
        VHDL code and then program the board if the result is successful.
        """
        self._current_state = STATE_SYNTHESIZING
        c = Compiler(self._compiling_files_path, self._compiling_tools_path, self._device_name.lower())
        # c.DEBUG = True
        content = base64.b64decode(file_content)

        done_already = c.is_same_as_last(content)

        if not done_already:
            if self._device_name.lower() == "fpga":
                # TODO: This is quite ugly. We make sure the Compilar class replaces some string to make the
                # UCF / augmented reality works.
                c.feed_vhdl(content, True, False)
            else:
                c.feed_vhdl(content, False, False)
            if DEBUG:
                print "[DBG]: VHDL fed. Now compiling."
            success = c.compileit()

        else:
            if DEBUG:
                print "[DBG]: VHDL is already available. Reusing."
            success = c.get_last_result()

            # TODO: Fix this. Wrong work-around around a bug, so that it works during
            # controlled circumstances.
            # if success is None: success = True

        if success is not None and not success:
            self._current_state = STATE_SYNTHESIZING_ERROR
            self._compiling_result = c.errors()
        else:
            # If we are using adaptive timing, modify it according to this last input.
            # TODO: Consider limiting the allowed range of variation, in order to dampen potential anomalies.
            elapsed = c.get_time_elapsed()
            if self._adaptive_time:
                self._programmer_time = elapsed

            targetfile = c.retrieve_targetfile()
            if DEBUG:
                print "[DBG]: Target file retrieved after successful compile. Now programming."
            c._compiling_result = "Synthesizing done."
            self._program_file_t(targetfile)
Ejemplo n.º 3
0
 def _handle_ucf_file(self, file_content, file_info):
     print os.getcwd()
     c = Compiler(self._compiling_files_path)
     content = base64.b64decode(file_content)
     c.feed_ucf(content)
Ejemplo n.º 4
0
    def _compile_program_file_t(self, file_content):
        """
        Running in its own thread, this method will compile the provided
        VHDL code and then program the board if the result is successful.
        """
        self._current_state = STATE_SYNTHESIZING
        c = Compiler(self._compiling_files_path, self._compiling_tools_path,
                     self._device_name.lower())
        # c.DEBUG = True
        content = base64.b64decode(file_content)

        done_already = c.is_same_as_last(content)

        if not done_already:
            if self._device_name.lower() == "fpga":
                # TODO: This is quite ugly. We make sure the Compilar class replaces some string to make the
                # UCF / augmented reality works.
                c.feed_vhdl(content, True, False)
            else:
                c.feed_vhdl(content, False, False)
            if DEBUG: print "[DBG]: VHDL fed. Now compiling."
            success = c.compileit()

        else:
            if DEBUG: print "[DBG]: VHDL is already available. Reusing."
            success = c.get_last_result()

            # TODO: Fix this. Wrong work-around around a bug, so that it works during
            # controlled circumstances.
            # if success is None: success = True

        if success is not None and not success:
            self._current_state = STATE_SYNTHESIZING_ERROR
            self._compiling_result = c.errors()
        else:
            # If we are using adaptive timing, modify it according to this last input.
            # TODO: Consider limiting the allowed range of variation, in order to dampen potential anomalies.
            elapsed = c.get_time_elapsed()
            if (self._adaptive_time):
                self._programmer_time = elapsed

            targetfile = c.retrieve_targetfile()
            if DEBUG:
                print "[DBG]: Target file retrieved after successful compile. Now programming."
            c._compiling_result = "Synthesizing done."
            self._program_file_t(targetfile)
Ejemplo n.º 5
0
 def _handle_ucf_file(self, file_content, file_info):
     print os.getcwd()
     c = Compiler(self._compiling_files_path)
     content = base64.b64decode(file_content)
     c.feed_ucf(content)