def test_tester_while3(target, simulator):
circ = TestArrayCircuit
tester = fault.Tester(circ)
tester.zero_inputs()
tester.poke(circ.I, 1)
tester.eval()
loop = tester._while(tester.peek(tester._circuit.O) == 0)
loop.poke(circ.I, 1)
loop.eval()
tester.expect(circ.O, 1)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_peek(target, simulator):
circ = TestBasicClkCircuit
tester = fault.Tester(circ, circ.CLK)
tester.poke(circ.I, 0)
tester.eval()
tester.expect(circ.O, 0)
check(tester.actions[0], Poke(circ.I, 0))
check(tester.actions[2], Expect(circ.O, 0))
tester.poke(circ.CLK, 0)
check(tester.actions[3], Poke(circ.CLK, 0))
tester.step()
check(tester.actions[4], Step(circ.CLK, 1))
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_file_io_chunk_size_4_big_endian(target, simulator):
with tempfile.TemporaryDirectory(dir=".") as _dir:
# determine absolute paths to file I/O locations
test_file_in = (Path(_dir) / 'test_file_in.raw').resolve()
test_file_out = (Path(_dir) / 'test_file_out.raw').resolve()
if test_file_out.exists():
test_file_out.unlink()
# create testbench
circ = TestUInt32Circuit
tester = fault.Tester(circ)
tester.zero_inputs()
file_in = tester.file_open(str(test_file_in),
"r",
chunk_size=4,
endianness="big")
file_out = tester.file_open(str(test_file_out),
"w",
chunk_size=4,
endianness="big")
loop = tester.loop(8)
value = loop.file_read(file_in)
loop.poke(circ.I, value)
loop.eval()
loop.expect(circ.O, loop.index)
loop.file_write(file_out, circ.O)
tester.file_close(file_in)
tester.file_close(file_out)
# write input
with open(test_file_in, "wb") as file:
for i in range(8):
file.write(bytes([0, 0, 0, i]))
# run simulation
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
# read output
with open(test_file_out, "rb") as file:
for i in range(8):
assert file.read(4) == bytes([0, 0, 0, i])
def test_tester_clock(target, simulator):
circ = TestPeekCircuit
tester = fault.Tester(circ)
tester.poke(circ.I, 0)
tester.expect(circ.O0, tester.peek(circ.O1))
check(tester.actions[0], Poke(circ.I, 0))
check(tester.actions[1], Expect(circ.O0, Peek(circ.O1)))
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target,
directory=_dir,
simulator=simulator,
magma_opts={"sv": True})
def test_term():
width = 11
T = Array[width, BitIn]
args = ['I', In(T), 'O', Out(T)]
testcircuit = DefineCircuit('Test_Term', *args)
wire(testcircuit.I, testcircuit.O)
term = TermAnyType(T)
t_const = DefineCoreirConst(width, 0)()
wire(t_const.O, term.I)
EndCircuit()
tester = fault.Tester(testcircuit)
tester.circuit.I = 2
tester.eval()
tester.circuit.O.expect(2)
compile_and_run(tester)
def test_ram_11_13():
width = 11
numOut = 13
T = Array[width, BitOut]
testcircuit = DefineRAMAnyType(T, numOut)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.WE = True
for i in range(numOut + 1):
tester.circuit.RADDR = i % numOut
tester.circuit.WADDR = i % numOut
tester.circuit.WDATA = i % numOut
tester.step(2)
tester.circuit.RDATA.expect(i % numOut)
compile_and_run(tester)
def test_poke_expect_var(target, simulator, T, value):
circ = TestArrayCircuit
tester = fault.Tester(circ)
tester.zero_inputs()
tester.eval()
v = tester.Var("v", T)
tester.poke(v, value)
tester.eval()
tester.poke(circ.I, v)
tester.eval()
tester.expect(circ.O, value)
tester.expect(circ.O, v)
with tempfile.TemporaryDirectory(dir=".") as _dir:
kwargs = {"target": target, "directory": _dir}
if target == "system-verilog":
kwargs["simulator"] = simulator
tester.compile_and_run(**kwargs)
def test_slice_wrapper(lo, hi):
width = 32
slice_wrapper = SliceWrapper(width, lo, hi)
slice_wrapper_circuit = slice_wrapper.circuit()
tester = fault.Tester(slice_wrapper_circuit)
for _ in range(10):
value = random.randint(0, (1 << width) - 1)
expected_value = (value >> lo) & ((1 << hi) - 1)
tester.poke(slice_wrapper_circuit.I, value)
tester.eval()
tester.expect(slice_wrapper_circuit.O, expected_value)
with tempfile.TemporaryDirectory() as tempdir:
tester.compile_and_run(target="verilator",
directory=tempdir,
magma_output="coreir-verilog",
flags=["-Wno-fatal"])
def test_tuple_circuit(target, simulator):
circ = TestTupleCircuit
tester = fault.Tester(circ)
tester.circuit.I = (4, 2)
tester.eval()
tester.circuit.O.expect((4, 2))
tester.circuit.I = {"a": 4, "b": 2}
tester.eval()
tester.circuit.O.expect({"a": 4, "b": 2})
with tempfile.TemporaryDirectory(dir=".") as _dir:
kwargs = {"target": target, "directory": _dir}
if target == "system-verilog":
kwargs["simulator"] = simulator
kwargs["magma_opts"] = {"sv": True}
tester.compile_and_run(**kwargs)
def test_tester_basic(target, simulator):
circ = TestBasicCircuit
tester = fault.Tester(circ)
tester.zero_inputs()
check(tester.actions[0], Poke(circ.I, 0))
tester.poke(circ.I, 1)
tester.eval()
tester.expect(circ.O, 1)
tester.print("%08x", circ.O)
check(tester.actions[1], Poke(circ.I, 1))
check(tester.actions[2], Eval())
check(tester.actions[3], Expect(circ.O, 1))
print(tester.actions[4])
print(Print("%08x", circ.O))
check(tester.actions[4], Print("%08x", circ.O))
tester.eval()
check(tester.actions[5], Eval())
tester.poke(circ.I, 0)
tester.eval()
tester.expect(circ.O, 0)
tester.poke(circ.I, True)
tester.eval()
tester.expect(circ.O, True)
tester.poke(circ.I, False)
tester.eval()
tester.expect(circ.O, False)
tester.poke(circ.I, False)
tester.eval()
tester.expect(circ.O, False)
tester.poke(circ.I, hwtypes.Bit(1))
tester.eval()
tester.expect(circ.O, hwtypes.Bit(1))
tester.poke(circ.I, hwtypes.Bit(0))
tester.eval()
tester.expect(circ.O, hwtypes.Bit(0))
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
tester.compile_and_run("coreir")
tester.clear()
assert tester.actions == []
def test_mux_with_default_wrapper(num_inputs, width, sel_bits, default):
if 2**sel_bits <= num_inputs:
with pytest.raises(ValueError) as pytest_e:
MuxWithDefaultWrapper(num_inputs, width, sel_bits, default)
assert False
expected_error = ValueError(f"(2 ^ sel_bits) must be > num_inputs "
f"(sel_bits={sel_bits}, "
f"num_inputs={num_inputs})")
assert pytest_e.type == type(expected_error)
assert repr(pytest_e.value) == repr(expected_error)
return
mux = MuxWithDefaultWrapper(num_inputs, width, sel_bits, default)
assert mux.num_inputs == num_inputs
assert mux.width == width
assert mux.sel_bits == sel_bits
assert mux.default == default
assert mux.name() == f"MuxWithDefaultWrapper_{num_inputs}_{width}"\
f"_{sel_bits}_{default}"
mux_circuit = mux.circuit()
tester = fault.Tester(mux_circuit)
inputs = [fault.random.random_bv(width) for _ in range(num_inputs)]
for i, input_ in enumerate(inputs):
tester.poke(mux_circuit.I[i], input_)
tester.poke(mux_circuit.EN, 1)
for i in range(num_inputs):
tester.poke(mux_circuit.S, BitVector(i, mux.sel_bits))
tester.eval()
tester.expect(mux_circuit.O, inputs[i])
for _ in range(10):
sel = choice(range(num_inputs, 2**sel_bits))
tester.poke(mux_circuit.S, BitVector(sel, mux.sel_bits))
tester.eval()
tester.expect(mux_circuit.O, default)
# Test that with EN=0, we get the default value, even with select being in
# [0, num_inputs).
tester.poke(mux_circuit.EN, 0)
for i in range(num_inputs):
tester.poke(mux_circuit.S, BitVector(i, mux.sel_bits))
tester.eval()
tester.expect(mux_circuit.O, default)
with tempfile.TemporaryDirectory() as tempdir:
tester.compile_and_run(directory=tempdir,
magma_output="coreir-verilog",
flags=["-Wno-fatal"])
def test_mux(mux_ctor, height):
width = 16
num_tests = 100
mux = mux_ctor(height, width)
mod_src = verilog(mux)
with tempfile.TemporaryDirectory() as tempdir:
filename = os.path.join(tempdir, mux.name + ".sv")
with open(filename, "w+") as f:
for value in mod_src.values():
f.write(value)
f.write("\n")
# import it as magma circuit
circuit = magma.DefineFromVerilogFile(filename,
target_modules=[mux.name],
shallow=True)[0]
tester = fault.Tester(circuit)
tester.zero_inputs()
test_data = []
for _ in range(num_tests):
data_point = []
for i in range(height):
data_point.append(BitVector.random(width))
# select
sel = random.randrange(height)
output = data_point[sel]
data_point += [sel, output]
test_data.append(data_point)
for entry in test_data:
for i in range(height):
tester.poke(circuit.interface["I{0}".format(i)], entry[i])
tester.poke(circuit.S, entry[height])
tester.eval()
tester.expect(circuit.O, entry[-1])
tester.compile_and_run(target="verilator",
skip_compile=True,
directory=tempdir,
flags=["-Wno-fatal"])
def test_inv_tf(target,
simulator,
n_steps=100,
vsup=1.5,
vil_rel=0.4,
vih_rel=0.6,
vol_rel=0.1,
voh_rel=0.9):
# declare circuit
class myinv(m.Circuit):
io = m.IO(in_=fault.RealIn,
out=fault.RealOut,
vdd=fault.RealIn,
vss=fault.RealIn)
# wrap if needed
if target == 'verilog-ams':
dut = fault.VAMSWrap(myinv)
else:
dut = myinv
# define the test
tester = fault.Tester(dut)
tester.poke(dut.vdd, vsup)
tester.poke(dut.vss, 0)
for k in range(n_steps):
in_ = k * vsup / (n_steps - 1)
tester.poke(dut.in_, in_)
tester.eval()
if in_ <= vil_rel * vsup:
tester.expect(dut.out, vsup, above=voh_rel * vsup)
elif in_ >= vih_rel * vsup:
tester.expect(dut.out, 0, below=vol_rel * vsup)
# set options
kwargs = dict(target=target,
simulator=simulator,
model_paths=[Path('tests/spice/myinv.sp').resolve()],
vsup=vsup,
tmp_dir=True)
if target == 'verilog-ams':
kwargs['use_spice'] = ['myinv']
# run the simulation
tester.compile_and_run(**kwargs)
def test_write_enable(backend):
height = 4
data_width = 4
addr_width = m.bitutils.clog2(height)
class _Main(m.Circuit):
name = f"test_regfile_enable_{backend}"
io = m.IO(write_addr=m.In(m.Bits[addr_width]),
write_data=m.In(m.Bits[data_width]),
write_enable=m.In(m.Enable),
read_addr=m.In(m.Bits[addr_width]),
read_data=m.Out(
m.Bits[data_width])) + m.ClockIO(has_async_reset=True)
reg_file = mantle.RegFileBuilder("my_regfile",
height,
data_width,
backend=backend)
reg_file.write(io.write_addr, io.write_data, enable=io.write_enable)
io.read_data @= reg_file[io.read_addr]
m.compile(f"build/test_regfile_enable_{backend}", _Main)
assert check_files_equal(__file__,
f"build/test_regfile_enable_{backend}.v",
f"gold/test_regfile_enable_{backend}.v")
tester = fault.Tester(_Main, _Main.CLK)
tester.circuit.CLK = 0
for i in range(4):
tester.circuit.write_enable = 1
tester.circuit.write_addr = i
tester.circuit.write_data = i
tester.step(2)
# Write enable low should not change the value
tester.circuit.write_enable = 0
tester.circuit.write_data = 0
tester.step(2)
for i in range(4):
tester.circuit.read_addr = i
tester.eval()
tester.circuit.read_data.expect(i)
build_dir = os.path.join(os.path.dirname(__file__), "build")
tester.compile_and_run(target="verilator",
directory=build_dir,
skip_compile=True,
flags=["-Wno-unused", "-Wno-undriven"])
def test_pass_through_mux_wrapper():
height = 1
width = 16
mux = MuxWrapper(height, width)
assert mux.height == height
assert mux.width == width
assert mux.name() == f"MuxWrapper_{height}_{width}"
mux_circuit = mux.circuit()
tester = fault.Tester(mux_circuit)
input_ = fault.random.random_bv(width)
tester.poke(mux_circuit.I[0], input_)
tester.eval()
tester.expect(mux_circuit.O, input_)
with tempfile.TemporaryDirectory() as tempdir:
tester.compile_and_run(directory=tempdir,
magma_output="coreir-verilog",
flags=["-Wno-fatal"])
def test_2_3_shared_sseq_2_tseq_3_3_flip_reshape():
"""
Tests reshape with both sseq and tseq on inside
"""
no = 3
io = 0
ni = 2
nii = 2
niii = 3
iiii = 3
input_type = ST_TSeq(
no, io, ST_SSeq(ni, ST_SSeq(nii, ST_TSeq(niii, iiii, ST_Int()))))
output_type = ST_SSeq(
ni, ST_TSeq(no, io, ST_SSeq(nii, ST_TSeq(niii, iiii, ST_Int()))))
graph = build_permutation_graph(input_type, output_type)
testcircuit = DefineReshape_ST(input_type, output_type)
tester = fault.Tester(testcircuit, testcircuit.CLK)
check_reshape(graph, 2, testcircuit.output_delay, tester, 1, 1)
def test_reduce_s_basic():
num_in = 4
num_iterations = 2
test_vals = [2,4,6,8,1,3,5,9]
outputs = [20,18]
red = DefineReduce_S(num_in, DefineAdd_Atom(), has_valid=True)
tester = fault.Tester(red, red.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
tester.print("clk: {}\n".format(i))
for j in range(num_in):
tester.circuit.I[j] = test_vals[i*num_in + j]
tester.step(2)
tester.circuit.valid_down.expect(1)
tester.circuit.O[0].expect(outputs[i])
compile_and_run(tester)
def test_rom_11_13():
width = 11
numOut = 13
T = Array[width, BitOut]
init = [builtins.tuple(int2seq(i)) for i in range(4, numOut+4)]
return
testcircuit = DefineROMAnyType(T, width, builtins.tuple(init))
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.RE = True
for i in range(numOut):
tester.circuit.RADDR = i
tester.step(2)
tester.circuit.RDATA.expect(i + 4)
compile_and_run(tester)
def test_tester_128(target, simulator):
circ = TestUInt128Circuit
tester = fault.Tester(circ)
expected = []
val = random.randint(0, (1 << 128) - 1)
tester.poke(circ.I, val)
tester.eval()
tester.expect(circ.O, val)
expected.append(Poke(circ.I, val))
expected.append(Eval())
expected.append(Expect(circ.O, val))
for i, exp in enumerate(expected):
check(tester.actions[i], exp)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_fault_shift_s():
num_in = 4
test_vals = [2, 5, 3, 8]
shift_amount = 2
in_type = ST_SSeq(num_in, ST_Int())
rshift = DefineShift_S(num_in, shift_amount, in_type.t, has_valid=True)
tester = fault.Tester(rshift, rshift.CLK)
tester.circuit.valid_up = 1
for i, val in enumerate(test_vals):
tester.circuit.I[i] = val
tester.eval()
for i, val in enumerate(test_vals[shift_amount:]):
tester.circuit.O[i + shift_amount].expect(test_vals[i])
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def run_conv_test(testcircuit, parallelism):
magma.compile("vBuild/" + testcircuit.name, testcircuit, output="coreir-verilog",
passes=["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst", "flattentypes", "flatten", "verifyconnectivity --noclkrst", "deletedeadinstances"],
namespaces=["aetherlinglib", "commonlib", "mantle", "coreir", "global"])
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.poke(testcircuit.valid_data_in, 1)
tester.poke(testcircuit.ready_data_out, 1)
tester.poke(testcircuit.CE, 1)
# these check the outputs, as there is a delay between feeding inputs in and getting the results back
for row in range(num_rows+20):
for col in range(0,num_cols, parallelism):
# a necessary adjustment as running tests for multiple clocks after inputting full image
# to get rest of the outputs
if row < num_rows:
for i in range(parallelism):
tester.poke(getattr(testcircuit, "I" + str(i)), image_matrix[row][col + i])
tester.eval()
tester.step(2)
tester.eval()
print_start_clock(tester)
print_nd_bit_array_port(tester, testcircuit.valid_data_out, "valid")
for i in range(parallelism):
print_nd_int_array_port(tester, getattr(testcircuit, "O" + str(i)), "O" + str(i))
print_end_clock(tester)
tester.compile_and_run(target="verilator", skip_compile=True, directory="vBuild/")
with open(get_fault_log(__file__, testcircuit.name)) as file:
results = eval("[" + file.read() + "]")
filtered_results = []
current_output = 0
for clk_result in results:
if clk_result['valid'] == 1:
current_output_row = current_output // num_rows
current_output_column = current_output % num_rows
for i in range(parallelism):
if current_output_row in valid_rows and current_output_column + i in valid_cols:
filtered_results.append(clk_result["O" + str(i)])
current_output += parallelism
if len(filtered_results) >= len(flattenedResults):
assert filtered_results[0:len(flattenedResults)] == flattenedResults
else:
assert filtered_results == flattenedResults
def test_shift_tn_inner_invalid_elem_invalid_v_always_true_no_ce():
num_in = [3, 2, 2]
test_vals = [i * 2 for i in range(num_in[0] * num_in[1] * num_in[2])]
shift_amount = 1
iis = (2, 1)
num_iterations = 2
testcircuit = DefineShift_TN(num_in[0], (2, 2),
0,
iis,
shift_amount,
ST_TSeq(1, 2, ST_Int()),
has_valid=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
for clk_outer in range(num_in[0]):
for clk_inner in range(num_in[1] + iis[0]):
for clk_ii in range(num_in[2] + iis[1]):
for clk_innermost in range(0, 3):
tester.print("clk_outer: {}\n".format(clk_outer))
tester.print("clk_inner: {}\n".format(clk_inner))
tester.print("clk_ii: {}\n".format(clk_ii))
val_idx = clk_outer * 4 + min(
clk_inner, num_in[1] - 1) * 2 + min(
clk_ii, num_in[2] - 1)
in_val = test_vals[val_idx] + i + (
0 if clk_inner < 2 and clk_ii < 2
and clk_innermost == 0 else 110)
tester.circuit.I = in_val
tester.print("I: {}\n".format(str(in_val)))
tester.eval()
tester.print("O: %d\n", tester.circuit.O)
#tester.print("inner_valid: %d\n", tester.circuit.inner_valid)
if val_idx >= shift_amount and clk_inner < 2 and clk_ii < 2 and clk_innermost == 0:
tester.circuit.O.expect(test_vals[val_idx -
shift_amount] +
i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_poke_bitwise_nested(target, simulator):
circ = TestNestedArraysCircuit
tester = fault.Tester(circ)
tester.circuit.I = 0
tester.eval()
tester.circuit.I[0][0] = 1
tester.circuit.I[1][1] = 1
tester.eval()
tester.circuit.O[0][0].expect(1)
tester.circuit.O[0][1].expect(0)
tester.circuit.O[1][0].expect(0)
tester.circuit.O[1][1].expect(1)
tester.assert_((tester.circuit.O[0] | tester.circuit.O[1]) == 0b11)
with tempfile.TemporaryDirectory(dir=".") as _dir:
_dir = "build"
kwargs = {"target": target, "directory": _dir}
if target == "system-verilog":
kwargs["simulator"] = simulator
tester.compile_and_run(**kwargs)
def test_poke_bitwise(target, simulator):
circ = TestArrayCircuit
tester = fault.Tester(circ)
tester.circuit.I = 0
tester.eval()
tester.circuit.I[0] = 1
tester.circuit.I[2] = 1
tester.eval()
tester.circuit.O[0].expect(1)
tester.circuit.O[1].expect(0)
tester.circuit.O[2].expect(1)
tester.circuit.I[1:] = 0b01
tester.eval()
tester.circuit.O[1:].expect(0b01)
with tempfile.TemporaryDirectory(dir=".") as _dir:
kwargs = {"target": target, "directory": _dir}
if target == "system-verilog":
kwargs["simulator"] = simulator
tester.compile_and_run(**kwargs)
def test_tester_loop(target, simulator):
circ = TestArrayCircuit
tester = fault.Tester(circ)
tester.zero_inputs()
loop = tester.loop(7)
loop.poke(circ.I, loop.index)
loop.eval()
loop.expect(circ.O, loop.index)
assert tester.actions[1].n_iter == 7
for actual, expected in zip(tester.actions[1].actions,
[Poke(circ.I, loop.index),
Eval(),
Expect(circ.O, loop.index)]):
check(actual, expected)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_nested_arrays_by_element(target, simulator):
circ = TestNestedArraysCircuit
tester = fault.Tester(circ)
expected = []
for i in range(3):
val = random.randint(0, (1 << 4) - 1)
tester.poke(circ.I[i], val)
tester.eval()
tester.expect(circ.O[i], val)
expected.append(Poke(circ.I[i], val))
expected.append(Eval())
expected.append(Expect(circ.O[i], val))
for i, exp in enumerate(expected):
check(tester.actions[i], exp)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_while_loop(target, simulator, n_cyc=3, n_bits=8):
class dut(m.Circuit):
name = 'clkdelay'
io = m.IO(
clk=m.In(m.Clock),
rst=m.In(m.Reset),
count=m.Out(m.Bits[n_bits]),
n_done=m.Out(m.Bit)
)
# instantiate the tester
tester = fault.Tester(dut, clock=dut.clk, reset=dut.rst)
tester.circuit.clk = 0
# reset
tester.sync_reset()
# check initial state
tester.expect(dut.n_done, 1)
tester.expect(dut.count, 0)
# wait for the loop to complete
tester.poke(dut.rst, 0)
loop = tester._while(dut.n_done)
debug_print(loop, dut)
loop.step()
loop.step()
debug_print(tester, dut)
# check final state
tester.expect(dut.count, n_cyc - 1)
tester.expect(dut.n_done, 0)
# run the test
tester.compile_and_run(
target=target,
simulator=simulator,
tmp_dir=True,
ext_libs=[Path('tests/verilog/clkdelay.sv').resolve()],
ext_model_file=True,
defines={'N_CYC': n_cyc, 'N_BITS': n_bits}
)
def base_lake_tester(config_path,
in_file_name,
out_file_name,
in_ports,
out_ports,
lt_dut,
stencil_valid=False):
configs = lt_dut.get_static_bitstream(config_path, in_file_name, out_file_name)
magma_dut = kts.util.to_magma(lt_dut,
flatten_array=True,
check_multiple_driver=False,
optimize_if=False,
check_flip_flop_always_ff=False)
tester = fault.Tester(magma_dut, magma_dut.clk)
configs_list = []
return lt_dut, configs, configs_list, magma_dut, tester
def test_not_onehot(use_sva):
class Main(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), x=m.In(m.Bit)) + m.ClockIO()
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.I)), "|-> ##1", io.x),
on=f.posedge(io.CLK))
else:
f.assert_(f.not_(f.onehot(io.I)) | f.implies | f.delay[1] | io.x,
on=f.posedge(io.CLK))
tester = f.Tester(Main, Main.CLK)
tester.circuit.I = 0xFF
tester.step(2)
tester.circuit.x = True
tester.circuit.I = 0x80
tester.step(2)
tester.circuit.I = 0x0
tester.circuit.x = False
tester.step(2)
tester.compile_and_run("system-verilog",
simulator="ncsim",
flags=["-sv"],
magma_opts={
"inline": True,
"drive_undriven": True,
"terminate_unused": True
})
tester.circuit.I = 0xFF
tester.step(2)
tester.circuit.x = 0
tester.step(2)
with pytest.raises(AssertionError):
tester.compile_and_run("system-verilog",
simulator="ncsim",
flags=["-sv"],
magma_opts={
"inline": True,
"drive_undriven": True,
"terminate_unused": True
})
def test_serialize_basic():
n = 5
i = 0
inputs = list(range(n))
num_iterations = 2
t = ST_Int()
ser = DefineSerialize(n, i, t)
tester = fault.Tester(ser, ser.CLK)
tester.circuit.valid_up = 1
tester.circuit.I = inputs
for clk in range(num_iterations * (n + i)):
tester.print("clk: {}\n".format(clk))
tester.step(2)
tester.circuit.valid_down.expect(1)
tester.circuit.O.expect(inputs[clk % n])
compile_and_run(tester)
