def test_initial_empty():
model = fifo.FIFO(depth_width=4)
model.elaborate()
sim = pymtl.SimulationTool(model)
sim.reset()
sim.cycle()
assert model.empty_o.value == 1, 'FIFO should be empty after reset'
assert model.full_o.value == 0, 'FIFO should not be full after reset'
def test_fifo_can_write():
# what does this depth width mean
model = fifo.FIFO(depth_width=1) # highset bit
model.elaborate()
sim = pymtl.SimulationTool(model)
sim.reset()
sim.cycle()
for i in xrange(2):
model.wr_data_i.value = i + 2
model.wr_en_i.value = 1
model.rd_en_i.value = 0
sim.cycle()
model.wr_en_i.value = 0
for wait_cycle in xrange(10):
if model.empty_o.value == 0:
break;
else:
sim.cycle()
assert model.empty_o.value == 0, 'FIFO empty_o should not be empty after write'
assert model.full_o.value == 1, 'FIFO full_o should be full after write to a 1 element FIFO'
model.rd_en_i.value = 1
sim.eval_combinational()
assert model.rd_data_o == 2, 'FIFO should read the correct value'
sim.cycle()
assert model.empty_o.value == 0, 'FIFO should not be empty after write'
assert model.full_o.value == 0, 'FIFO should not be full in the next cycle'
sim.eval_combinational()
assert model.rd_data_o == 3, 'FIFO should read the correct value'
sim.cycle()
assert model.empty_o.value == 1, 'FIFO should be empty in the next cycle'
assert model.full_o.value == 0, 'FIFO should not be full in the next cycle'
model.rd_en_i.value = 0
sim.cycle()
assert model.empty_o.value == 1, 'FIFO empty_o should be true'
def test_initial_empty():
pyrtl.reset_working_block()
model = fifo.FIFO(depth_width=4)
tracer = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=tracer)
sim.step({
'wr_data_i': 0,
'wr_en_i': 0,
'rd_en_i': 0,
'reset' : 1,
})
sim.step({
'wr_data_i': 0,
'wr_en_i': 0,
'rd_en_i': 0,
'reset' : 0,
})
assert tracer.trace['empty_o'][-1] == 1, 'FIFO should be empty after reset'
assert tracer.trace['full_o'][-1] == 0, 'FIFO should not be full after reset'
def initBuffer(self, bufferDepth=8):
return fifo.FIFO(int(bufferDepth), blockOnFull=False)
import fifo
import lru
import opt
myFIFO = fifo.FIFO()
myLRU = lru.LRU()
myOPT = opt.OPT()
print("FIFO STARTS HERE")
print(
"==============================================================================================================="
)
for i in range(1, 31):
myFIFO.runFIFOAlgo(i)
print(
"==============================================================================================================="
)
print()
print("LRU STARTS HERE")
print(
"==============================================================================================================="
)
for i in range(1, 31):
myLRU.runLRUAlgo(i)
print(
"==============================================================================================================="
)
print()
print("OPT STARTS HERE")
print(
"==============================================================================================================="
def test_fifo_can_read_write():
pyrtl.reset_working_block()
model = fifo.FIFO(depth_width=1)
tracer = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=tracer)
sim.step({
'wr_data_i': 0,
'wr_en_i': 0,
'rd_en_i': 0,
'reset' : 1,
})
for i in xrange(2):
sim.step({
'wr_data_i': i + 2,
'wr_en_i': 1,
'rd_en_i': 0,
'reset' : 0,
})
for wait_cycle in xrange(10):
sim.step({
'wr_data_i': 0x3,
'wr_en_i': 0,
'rd_en_i': 0,
'reset' : 0,
})
if tracer.trace['empty_o'][-1] == 0:
break
assert tracer.trace['empty_o'][-1] == 0, 'FIFO empty_o should not be empty after write'
assert tracer.trace['full_o'][-1] == 1, 'FIFO should be full'
sim.step({
'wr_data_i': 0x0,
'wr_en_i': 0,
'rd_en_i': 1,
'reset' : 0
})
assert tracer.trace['empty_o'][-1] == 0, 'FIFO empty_o should not be empty after write'
assert tracer.trace['full_o'][-1] == 1, 'FIFO should not be full in the next cycle'
assert tracer.trace['rd_data_o'][-1] == 2, 'FIFO should read the correct value'
sim.step({
'wr_data_i': 0x0,
'wr_en_i': 0,
'rd_en_i': 1,
'reset' : 0
})
assert tracer.trace['empty_o'][-1] == 0, 'FIFO empty_o should only be true in the next cycle'
assert tracer.trace['full_o'][-1] == 0, 'FIFO should not be full after a read'
assert tracer.trace['rd_data_o'][-1] == 3, 'FIFO should read the correct value'
sim.step({
'wr_data_i': 0x0,
'wr_en_i': 0,
'rd_en_i': 0,
'reset' : 0
})
assert tracer.trace['empty_o'][-1] == 1, 'FIFO empty_o should be true'