def step_resnet50_set_fifo_depths(model: ModelWrapper,
cfg: DataflowBuildConfig):
"""
Depending on the auto_fifo_depths setting, do one of the following:
* if auto_fifo_depths=True: Run the `InsertAndSetFIFODepths` transformation
to attempt to determine the FIFO sizes that provide full throughput. Involves
running stitched-IP rtlsim and may take a long time.
* if auto_fifo_depths=False: Assume the folding config file contains FIFO
sizes as well. Runs the `InsertFIFO` transformation, then
`ApplyConfig(cfg.folding_config_file)`, and finally `RemoveShallowFIFOs`.
Coherency with config file node naming is ensured by calling
`GiveUniqueNodeNames`.
"""
if cfg.auto_fifo_depths:
model = model.transform(
InsertAndSetFIFODepths(
cfg._resolve_fpga_part(),
cfg._resolve_hls_clk_period(),
vivado_ram_style=cfg.large_fifo_mem_style.value,
))
else:
# assume folding cfg json contains FIFO sizes too
# insert DWCs, FIFOs and run ApplyConfig once more
model = model.transform(InsertDWC())
# need to make sure all FIFOs are created so that their depth can be
# set by ApplyConfig, so create_shallow_fifos=True
model = model.transform(InsertFIFO(create_shallow_fifos=True))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
if cfg.folding_config_file is not None:
model = model.transform(ApplyConfig(cfg.folding_config_file))
# remove any shallow FIFOs
model = model.transform(RemoveShallowFIFOs())
# extract the final configuration and save it as json
hw_attrs = [
"PE",
"SIMD",
"ram_style",
"depth",
"impl_style",
"resType",
"mem_mode",
"runtime_writeable_weights",
]
extract_model_config_to_json(model,
cfg.output_dir + "/final_hw_config.json",
hw_attrs)
# after FIFOs are ready to go, call PrepareIP and HLSSynthIP again
# this will only run for the new nodes (e.g. FIFOs and DWCs)
model = model.transform(
PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()))
model = model.transform(HLSSynthIP())
model = model.transform(ReplaceVerilogRelPaths())
return model
def step_hls_codegen(model: ModelWrapper, cfg: DataflowBuildConfig):
"Generate Vivado HLS code to prepare HLSCustomOp nodes for IP generation."
model = model.transform(
PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period())
)
return model
def step_hls_ipgen(model: ModelWrapper, cfg: DataflowBuildConfig):
"Run Vivado HLS synthesis on any HLSCustomOp nodes to generate IP blocks."
model = model.transform(
PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()))
model = model.transform(HLSSynthIP())
model = model.transform(ReplaceVerilogRelPaths())
report_dir = cfg.output_dir + "/report"
os.makedirs(report_dir, exist_ok=True)
estimate_layer_resources_hls = model.analysis(hls_synth_res_estimation)
with open(report_dir + "/estimate_layer_resources_hls.json", "w") as f:
json.dump(estimate_layer_resources_hls, f, indent=2)
return model
