def gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5, srcDir):
if args.platform == 'tsmc65lp':
r_netlist = open(srcDir + "/TEMP_ANALOG_test.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/TEMP_ANALOG.nl.v", "w")
if args.platform == 'gf12lp':
r_netlist = open(srcDir + "/TEMP_ANALOG_generic.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/TEMP_ANALOG.nl.v", "w")
netmap1 = function.netmap() #modify here
netmap1.get_net('nn', None, 1, int(ninv), 1)
netmap1.get_net('n0', None, int(ninv), int(ninv), 1)
netmap1.get_net('na', aux1, 1, 1, 1)
netmap1.get_net('nb', aux2, 0, int(ninv) - 2, 1)
netmap1.get_net('ni', None, 0, int(ninv) - 2, 1)
netmap1.get_net('n1', None, 1, int(ninv) - 1, 1)
netmap1.get_net('n2', None, 2, int(ninv), 1)
netmap1.get_net('ng', aux2, 1, 1, 1)
netmap1.get_net('n3', None, int(ninv), int(ninv), 1)
netmap1.get_net('nk', aux2, 1, 1, 1)
netmap1.get_net('n4', None, int(ninv), int(ninv), 1)
netmap1.get_net('nm', aux2, 1, 1, 1)
netmap1.get_net('np', aux3, 1, 1, 1)
netmap1.get_net('nc', aux3, 1, 1, 1)
netmap1.get_net('nd', aux4, 1, 1, 1)
netmap1.get_net('ne', aux4, 1, 1, 1)
netmap1.get_net('nf', aux5, 0, int(nhead) - 1, 1)
netmap1.get_net('nh', None, 0, int(nhead) - 1, 1)
for line in lines:
netmap1.printline(line, w_netlist)
def gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5):
r_netlist = open("flow/src/TEMP_ANALOG_test.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open("flow/src/TEMP_ANALOG.nl.v", "w")
netmap1 = function.netmap() #modify here
netmap1.get_net('nn', None, 1, int(ninv), 1)
netmap1.get_net('n0', None, int(ninv), int(ninv), 1)
netmap1.get_net('na', aux1, 1, 1, 1)
netmap1.get_net('nb', aux2, 0, int(ninv) - 2, 1)
netmap1.get_net('ni', None, 0, int(ninv) - 2, 1)
netmap1.get_net('n1', None, 1, int(ninv) - 1, 1)
netmap1.get_net('n2', None, 2, int(ninv), 1)
netmap1.get_net('ng', aux2, 1, 1, 1)
netmap1.get_net('n3', None, int(ninv), int(ninv), 1)
netmap1.get_net('nk', aux2, 1, 1, 1)
netmap1.get_net('n4', None, int(ninv), int(ninv), 1)
netmap1.get_net('nm', aux2, 1, 1, 1)
netmap1.get_net('np', aux3, 1, 1, 1)
netmap1.get_net('nc', aux3, 1, 1, 1)
netmap1.get_net('nd', aux4, 1, 1, 1)
netmap1.get_net('ne', aux4, 1, 1, 1)
netmap1.get_net('nf', aux5, 0, int(nhead) - 1, 1)
netmap1.get_net('nh', None, 0, int(nhead) - 1, 1)
for line in lines:
netmap1.printline(line, w_netlist)
def gen_cdc_cnt(aux1, aux2, aux3, aux4, srcDir):
r_netlist = open(srcDir + "/CDCW_CNT_template.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/CDCW_CNT.v", "w")
netmap6 = function.netmap() #modify here
netmap6.get_net('na', aux1, 1, 1, 1)
for i in range(0, 2):
netmap6.get_net('nb', aux2, 1, 1, 1)
netmap6.get_net('nc', aux3, 1, 1, 1)
netmap6.get_net('nd', aux4, 1, 1, 1)
for line in lines:
netmap6.printline(line, w_netlist)
def gen_cdc_analog(npre, aux1, aux2, srcDir):
r_netlist = open(srcDir + "/CDC_ANALOG_template.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/CDC_ANALOG.nl.v", "w")
netmap5 = function.netmap() #modify here
netmap5.get_net('na', aux1, 1, npre, 1)
netmap5.get_net('ni', None, 1, npre, 1)
for i in range(0, 2):
netmap5.get_net('nb', aux2, 1, 1, 1)
for line in lines:
netmap5.printline(line, w_netlist)
def gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5, srcDir):
r_netlist = open(srcDir + "/TEMP_ANALOG_lv.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/TEMP_ANALOG_lv.nl.v", "w")
port = 'X'
slc_cell = "SLC a_lc_0(.IN(out), .INB(outb), .VOUT(lc_0));"
netmap1 = function.netmap() #modify here
netmap1.get_net('nn', None, 1, int(ninv), 1)
netmap1.get_net('n0', None, int(ninv), int(ninv), 1)
netmap1.get_net('na', aux1, 1, 1, 1)
netmap1.get_net('nb', aux2, 0, int(ninv) - 2, 1)
netmap1.get_net('ni', None, 0, int(ninv) - 2, 1)
netmap1.get_net('n1', None, 1, int(ninv) - 1, 1)
netmap1.get_net('n2', None, 2, int(ninv), 1)
netmap1.get_net('ng', aux2, 1, 1, 1)
netmap1.get_net('n3', None, int(ninv), int(ninv), 1)
netmap1.get_net('nk', aux2, 1, 1, 1)
netmap1.get_net('n4', None, int(ninv), int(ninv), 1)
netmap1.get_net('nm', aux2, 1, 1, 1)
netmap1.get_net('np', aux3, 1, 1, 1)
netmap1.get_net('nc', aux3, 1, 1, 1)
netmap1.get_net('nd', aux4, 1, 1, 1)
netmap1.get_net('ne', aux4, 1, 1, 1)
for line in lines:
line = line.replace("nbout", port)
netmap1.printline(line, w_netlist)
r_netlist = open(srcDir + "/TEMP_ANALOG_hv.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/TEMP_ANALOG_hv.nl.v", "w")
netmap1.get_net('nf', aux5, 0, int(nhead) - 1, 1)
netmap1.get_net('nh', None, 0, int(nhead) - 1, 1)
netmap1.get_net('no', aux3, 1, 1, 1)
for line in lines:
line = line.replace("SLC", slc_cell)
line = line.replace("nbout", port)
netmap1.printline(line, w_netlist)
r_netlist = open(srcDir + "/counter_generic.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/counter.v", "w")
netmap1.get_net('np', aux3, 1, 1, 1)
for line in lines:
line = line.replace("nbout", port)
netmap1.printline(line, w_netlist)
return
def gen_cdc_top(aux1, aux2, srcDir):
r_netlist = open(srcDir + "/CDC_template.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/cdcInst.v", "w")
netmap7 = function.netmap() #modify here
for i in range(0, 16):
netmap7.get_net('na', aux1, 1, 1, 1)
for i in range(0, 3):
netmap7.get_net('nb', aux2, 1, 1, 1)
for i in range(0, 2):
netmap7.get_net('nc', aux1, 1, 1, 1)
for line in lines:
netmap7.printline(line, w_netlist)
def gen_cdc_dly_comp(aux1, aux2, aux3, aux4, aux5, srcDir):
r_netlist = open(srcDir + "/DLY_COMP_template.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/DLY_COMP.nl.v", "w")
netmap4 = function.netmap() #modify here
for i in range(0, 5):
netmap4.get_net('na', aux1, 1, 1, 1)
for i in range(0, 2):
netmap4.get_net('nb', aux2, 1, 1, 1)
for i in range(0, 2):
netmap4.get_net('nc', aux3, 1, 1, 1)
netmap4.get_net('nd', aux4, 1, 1, 1)
netmap4.get_net('nf', aux5, 1, 1, 1)
for line in lines:
netmap4.printline(line, w_netlist)
def gen_cdc_nxt_edge_gen(aux1, aux2, aux3, aux4, srcDir):
r_netlist = open(srcDir + "/NEXT_EDGE_GEN_template.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/NEXT_EDGE_GEN.nl.v", "w")
netmap3 = function.netmap() #modify here
for i in range(0, 12):
netmap3.get_net('na', aux1, 1, 1, 1)
for i in range(0, 4):
netmap3.get_net('nb', aux2, 1, 1, 1)
for i in range(0, 8):
netmap3.get_net('nc', aux3, 1, 1, 1)
for i in range(0, 2):
netmap3.get_net('nd', aux4, 1, 1, 1)
for line in lines:
netmap3.printline(line, w_netlist)
def gen_cdc_invchainiso(ninv, aux1, aux2, srcDir):
r_netlist = open(srcDir + "/INVCHAIN_ISOVDD_template.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/INVCHAIN_ISOVDD.nl.v", "w")
netmap1 = function.netmap() #modify here
netmap1.get_net('nn', None, 1, ninv, 1)
netmap1.get_net('na', aux1, 1, 1, 1)
netmap1.get_net('nb', aux1, 1, ninv - 1, 1)
netmap1.get_net('ni', None, 1, ninv - 1, 1)
netmap1.get_net('n1', None, 1, ninv - 1, 1)
netmap1.get_net('n2', None, 2, ninv, 1)
netmap1.get_net('nc', aux2, 1, 1, 1)
netmap1.get_net('n3', None, ninv, ninv, 1)
for line in lines:
netmap1.printline(line, w_netlist)
def gen_cdc_invchain(ninv, aux1, aux2, srcDir):
r_netlist = open(srcDir + "/CDC_ANALOG2_template.nl.v", "r")
lines = list(r_netlist.readlines())
w_netlist = open(srcDir + "/CDC_ANALOG2.nl.v", "w")
netmap2 = function.netmap() #modify here
netmap2.get_net('nn', None, 1, ninv, 1)
netmap2.get_net('na', aux1, 1, 1, 1)
netmap2.get_net('nb', aux1, 1, ninv - 1, 1)
netmap2.get_net('ni', None, 1, ninv - 1, 1)
netmap2.get_net('n1', None, 1, ninv - 1, 1)
netmap2.get_net('n2', None, 2, ninv, 1)
netmap2.get_net('nc', aux2, 1, 1, 1)
netmap2.get_net('n3', None, ninv, ninv, 1)
for line in lines:
netmap2.printline(line, w_netlist)
def gen_temp_netlist(dir_name, ninv, nhead):
r_netlist = open("./TEMP_net_template.sp", "r")
lines = list(r_netlist.readlines())
w_netlist = open(
"./%s/inv%d_header%d/TEMP_stage%dheader%d.sp" %
(dir_name, ninv, nhead, ninv, nhead), "w")
netmap1 = function.netmap() #modify here
netmap1.get_net('x1', None, 1, 1, 1)
netmap1.get_net('n0', None, ninv + 1, ninv + 1, 1)
netmap1.get_net('n1', None, 1, 1, 1)
netmap1.get_net('x2', None, 1, ninv, 1)
netmap1.get_net('n2', None, 1, ninv, 1)
netmap1.get_net('n3', None, 2, ninv + 1, 1)
netmap1.get_net('x3', None, 1, 1, 1)
netmap1.get_net('n4', None, ninv + 1, ninv + 1, 1)
netmap1.get_net('x4', None, 1, nhead, 1)
for line in lines:
netmap1.printline(line, w_netlist)
def gen_SC_netlist(CON, PD, aux1,srcDir):
r_netlist=open(srcDir + "/SC_AUTO_test.nl.v","r")
lines=list(r_netlist.readlines())
w_netlist=open(srcDir + "/SC_AUTO.nl.v","w")
N2 = ' '
N3 = ' '
P2 = 'low'
P3 = 'low'
vss2 = 'VSS'
vdd2 = 'VDD'
vss3 = 'VSS'
vdd3 = 'VDD'
if CON == 0.111 or CON == 0.101 or CON == 0.011 or CON == 0.001:
N2 = ' '
N3 = ' '
if CON == 0.111 or CON == 0.011:
P2 = 'high'
vss2 = 'VOUT'
vdd2 = 'VDD'
else:
P2 = 'low'
vss2 = 'VSS'
vdd2 = 'VOUT'
if CON == 0.111 or CON == 0.101:
P3 = 'high'
vss3 = 'VOUT2'
vdd3 = 'VDD'
else:
P3 = 'low'
vss3 = 'VSS'
vdd3 = 'VOUT2'
elif CON == 0.11 or CON == 0.01 :
N2 = ' '
N3 = '//'
if CON == 0.11:
P2 = 'high'
vss2 = 'VOUT'
vdd2 = 'VDD'
else:
P2 = 'low'
vss2 = 'VSS'
vdd2 = 'VOUT'
elif CON == 0.1:
N2 = '//'
N3 = '//'
else:
print('stage error')
netmap1=function.netmap() #modify here
netmap1.get_net('c1',aux1,1,PD,1)
netmap1.get_net('ni',None,1,PD,1)
netmap1.get_net('s2',N2,1,2*PD,1)
netmap1.get_net('c2',aux1,1,2*PD,1)
netmap1.get_net('u2',P2,1,2*PD,1)
netmap1.get_net('nj',None,1,2*PD,1)
netmap1.get_net('g2',vss2,1,2*PD,1)
netmap1.get_net('d2',vdd2,1,2*PD,1)
netmap1.get_net('s3',N3,1,4*PD,1)
netmap1.get_net('c3',aux1,1,4*PD,1)
netmap1.get_net('u3',P3,1,4*PD,1)
netmap1.get_net('nk',None,1,4*PD,1)
netmap1.get_net('g3',vss3,1,4*PD,1)
netmap1.get_net('d3',vdd3,1,4*PD,1)
for line in lines:
netmap1.printline(line,w_netlist)
