class Comparator: def __init__(self, inputs, n, name=None): if name is None: name = f"Comparator{n}" self.output = None self.inputs = inputs self.n = n self.name = name self.build() def build(self): xors = [] for i in range(self.n): xors.append(Xor((self.inputs[0][i], self.inputs[1][i]), f"{self.name}_xor{i}")) or0 = Or(tuple(xors), f"{self.name}_or0") self.output = Not(or0, f"{self.name}_not") def logic(self, depend=None): if depend is None: depend = [] if self in depend: return self.output.output depend.append(self) self.output.logic(depend) return self.output.output def __repr__(self): return f"{self.name}: {self.output.output}"
def alu_control(f0, f1, f2, f3, aluop0, aluop1): op3 = And((Not(aluop0), aluop0)) op2 = Or((aluop0, And((aluop1, f1)))) op1 = Or((Not(f2), Not(aluop1))) op0 = And((aluop1, Or(f3, f0))) return { op0: op0, op1: op1, op2: op2, op3: op3 }
def build(self): xors = [] for i in range(self.n): xors.append(Xor((self.inputs[0][i], self.inputs[1][i]), f"{self.name}_xor{i}")) or0 = Or(tuple(xors), f"{self.name}_or0") self.output = Not(or0, f"{self.name}_not")
def build(self): s1 = self.selectors[0] s0 = self.selectors[1] s0p = Not(s0, f"{self.name}_s0p") s1p = Not(s1, f"{self.name}_s1p") and0 = And((s1p, s0p, self.inputs[0]), f"{self.name}_and0") and1 = And((s1p, s0, self.inputs[1]), f"{self.name}_and1") and2 = And((s1, s0p, self.inputs[2]), f"{self.name}_and2") and3 = And((s1, s0, self.inputs[3]), f"{self.name}_and3") or0 = Or((and0, and1, and2, and3), f"{self.name}_or0") self.output = or0
def build(self): not0 = Not(self.input, f"{self.name}_not0") and1 = And((not0, self.clock), f"{self.name}_and1") and2 = And((self.input, self.clock), f"{self.name}_and2") or1 = Or(None, f"{self.name}_or1") or2 = Or(None, f"{self.name}_or2") not1 = Not(or1, f"{self.name}_not1") not2 = Not(or2, f"{self.name}_not2") or1.set_inputs((not2, and1)) or2.set_inputs((not1, and2)) self.output = not1 self.outputp = not2
def build(self): s = [] sp = [] for i in range(self.n): s.append(self.selectors[len(self.selectors) - 2 - self.n + i] if self.reverse == True else self.selectors[i]) sp.append( Not( self.selectors[len(self.selectors) - 2 - self.n + i] if self.reverse == True else self.selectors[i], f"{self.name}_sp{i}")) ands = [] for i in range(2**self.n): i_bin = bin(i)[2:].zfill(self.n) self.i_bin = i_bin ands.append( And( tuple([ s[j] if i_bin[j] == '1' else sp[j] for j in range(self.n) ]) + (self.inputs[i], ), f"{self.name}_and{i}")) or0 = Or(tuple(ands), f"{self.name}_or0") self.output = or0
def build(self): and0 = And( (self.inputs[0], Not(self.selectors[0], f"{self.name}_s0p")), f"{self.name}_and0") and1 = And((self.inputs[1], self.selectors[0]), f"{self.name}_and1") or0 = Or((and0, and1), f"{self.name}_or0") self.output = or0
def build(self): if not D_FlipFlop.GATE_LVL: return not1 = Not(self.clock, f"{self.name}_M_ncp") self.master = D_Latch(not1, self.input, f"{self.name}_M") # Master self.slave = D_Latch(self.clock, self.master, f"{self.name}_S") # Slave self.output = self.slave.output self.outputp = self.slave.outputp
def test2(): clock = Signal() d1 = D_FlipFlop(clock, None, "d1") not1 = Not(d1, "not") d1.set_input(not1) d1.set() for _ in range(20): clock.pulse() d1.logic() print(d1)
def johnson_counter(n=100): clock = Signal() bits = [D_FlipFlop(clock, None, f"d{i}") for i in range(n)] for i in range(1, n): bits[i].set_input(bits[i - 1]) bits[i].reset() bits[0].set_input(Not(bits[-1], "not")) bits[0].reset() for _ in range(4 * n): clock.pulse() bits[0].logic() print("".join([str(b.q()) for b in bits]))
def build(self): i = [] ip = [] for j in range(self.n): i.append(self.inputs[j]) ip.append(Not(self.inputs[j], f"{self.name}_sp{j}")) ands = [] for j in range(2**self.n): j_bin = bin(j)[2:].zfill(self.n) ands.append( And( tuple([ i[k] if j_bin[k] == '1' else ip[k] for k in range(self.n) ]), f"{self.name}_and{j}")) self.outputs = ands
def generate_control(opcode): Op5, Op4, Op3, Op2, Op1, Op0 = int_to_logic(opcode[0]), \ int_to_logic(opcode[1]), int_to_logic(opcode[2]), int_to_logic(opcode[3]), \ int_to_logic(opcode[4]), int_to_logic(opcode[5]) r_format = And((Not(Op5), Not(Op4), Not(Op3), Not(Op2), Not(Op1), Not(Op0)), "r_format") lw = And((Op5, Not(Op4), Not(Op3), Not(Op2), Op1, Op0)) sw = And((Op5, Not(Op4), Op3, Not(Op2), Op1, Op0)) beq = And((Not(Op5), Not(Op4), Not(Op3), Op2, Not(Op1), Not(Op0))) reg_dst = r_format alu_src = Or((lw, sw)) mem_to_reg = lw reg_write = Or((r_format, lw)) mem_read = lw mem_write = sw branch = beq alu_op1 = r_format alu_op0 = beq return {"reg_dst": reg_dst, "alu_src": alu_src, "mem_to_reg": mem_to_reg, "reg_write": reg_write, "mem_read": mem_read, "mem_write": mem_write , "branch": branch, "alu_op1": alu_op1, "alu_op0": alu_op0}