def __init__(self, platform, with_analyzer=False, with_loopback=False):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32, csr_address_width=15, # required for flash spi
integrated_rom_size=0,
integrated_sram_size=0x8000,
with_uart=False,
ident="USB2Sniffer design",
with_timer=False
)
self.submodules.crg = _CRG(platform)
# flash spi
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(clk_freq/25e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram fifo
depth = 32 * 1024 * 1024
self.submodules.dramfifo = ResetInserter()(LiteDRAMFIFO([("data", 32)], depth, 0,
self.sdram.crossbar, preserve_first_last=False))
self.submodules.hugefifo = ResetInserter()(stream.SyncFIFO([("data", 32)], 512))
# debug wishbone
self.add_cpu(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3e6))
self.add_wb_master(self.cpu.wishbone)
# usb phy
usb_pads = platform.request("usb_fifo")
self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024)
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
else:
# usb core
self.submodules.usb_core = USBCore(self.usb_phy, clk_freq)
# usb <--> wishbone
self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# ulpi switch
ulpi_sw = platform.request("ulpi_sw")
self.submodules.ulpi_sw_oe_n = GPIOOut(ulpi_sw.oe_n)
self.submodules.ulpi_sw_s = GPIOOut(ulpi_sw.s)
# ulpi 0
self.submodules.ulpi_phy0 = ULPIPHY(platform.request("ulpi", 0), cd="ulpi0")
self.submodules.ulpi_core0 = ULPICore(self.ulpi_phy0)
# packer0
self.submodules.overflow0 = OverflowMeter(ulpi_cmd_description(8, 1))
self.submodules.iticore0 = ITICore()
self.submodules.fifo0 = ResetInserter()(stream.SyncFIFO([("data", 40), ("len", 2)], 16))
self.submodules.conv40320 = Conv4032()
# ulpi 1
self.submodules.ulpi_phy1 = ULPIPHY(platform.request("ulpi", 1), cd="ulpi1")
self.submodules.ulpi_core1 = ULPICore(self.ulpi_phy1)
# usb <--> ulpi0
self.submodules.wrapcore0 = WrapCore(self.usb_core, self.usb_map["ulpi0"])
self.comb += [
self.ulpi_core0.source.connect(self.overflow0.sink),
self.overflow0.source.connect(self.iticore0.sink),
self.iticore0.source.connect(self.fifo0.sink),
self.fifo0.source.connect(self.conv40320.sink),
self.conv40320.source.connect(self.hugefifo.sink),
self.hugefifo.source.connect(self.dramfifo.sink),
self.dramfifo.source.connect(self.wrapcore0.sink),
]
# reset manager
self.rst_manager = ResetManager([self.iticore0, self.fifo0,
self.conv40320, self.hugefifo,
self.dramfifo, self.wrapcore0])
# leds
led0 = platform.request("rgb_led", 0)
self.submodules.blinker0 = BlinkerRGB(led0,
self.etherbone.packet.tx.source.valid,
0, self.etherbone.packet.rx.sink.valid)
led1 = platform.request("rgb_led", 1)
self.submodules.blinker1 = BlinkerRGB(led1,
self.ulpi_core0.source.valid,
0, self.wrapcore0.sender.source.valid)
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.crg.cd_usb.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0)
if with_analyzer:
analyzer_signals = [
self.ulpi_core0.source.valid,
self.ulpi_core0.source.ready,
self.ulpi_core0.source.data,
self.iticore0.source.valid,
self.iticore0.source.ready,
self.iticore0.source.data,
self.fifo.source.valid,
self.fifo.source.ready,
self.fifo.source.data,
self.wrapcore0.sender.source.valid,
self.wrapcore0.sender.source.ready,
self.wrapcore0.sender.source.data,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, clock_domain="sys")
def __init__(self, platform, with_analyzer=True, with_loopback=False):
sys_clk_freq = int(100e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="PCIe Screamer",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Serial Wishbone Bridge -------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=3e6)
self.add_wb_master(self.bridge.wishbone)
# PCIe PHY ---------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"))
self.add_csr("pcie_phy")
# USB FT601 PHY ----------------------------------------------------------------------------
self.submodules.usb_phy = FT601Sync(platform.request("usb_fifo"),
dw=32,
timeout=1024)
# USB Loopback -----------------------------------------------------------------------------
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(
phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
# USB Core ---------------------------------------------------------------------------------
else:
self.submodules.usb_core = USBCore(self.usb_phy, sys_clk_freq)
# USB <--> Wishbone --------------------------------------------------------------------
self.submodules.etherbone = Etherbone(self.usb_core,
self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# USB <--> TLP -------------------------------------------------------------------------
self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"])
self.comb += [
self.pcie_phy.source.connect(self.tlp.sender.sink),
self.tlp.receiver.source.connect(self.pcie_phy.sink)
]
# Wishbone --> MSI -------------------------------------------------------------------------
self.submodules.msi = MSI()
self.comb += self.msi.source.connect(self.pcie_phy.msi)
self.add_csr("msi")
# Led blink --------------------------------------------------------------------------------
usb_counter = Signal(32)
self.sync.usb += usb_counter.eq(usb_counter + 1)
self.comb += platform.request("user_led", 0).eq(usb_counter[26])
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.pcie_phy.sink,
self.pcie_phy.source,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 1024, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
platform,
with_cpu=False,
with_analyzer=True,
with_loopback=False):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type="lm32" if with_cpu else None,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_sram_size=0x8000,
with_uart=with_cpu,
ident="PCIe Injector example design",
with_timer=with_cpu)
self.submodules.crg = _CRG(platform)
if not with_cpu:
# use serial as wishbone bridge when no cpu
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=3000000))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# pcie endpoint
self.submodules.pciephy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
cd="sys")
# usb core
usb_pads = platform.request("usb_fifo")
# self.submodules.usb_phy = FT245PHYSynchronous(usb_pads, clk_freq, fifo_depth=16)
self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024)
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(
phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
else:
self.submodules.usb_core = USBCore(self.usb_phy, clk_freq)
# usb <--> wishbone
self.submodules.etherbone = Etherbone(self.usb_core,
self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# usb <--> tlp
self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"])
self.comb += [
self.pciephy.source.connect(self.tlp.sender.sink),
self.tlp.receiver.source.connect(self.pciephy.sink)
]
# wishbone --> msi
self.submodules.msi = MSI()
self.comb += self.msi.source.connect(self.pciephy.msi)
# led blink
usb_counter = Signal(32)
self.sync.usb += usb_counter.eq(usb_counter + 1)
self.comb += platform.request("user_led", 0).eq(usb_counter[26])
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.crg.cd_usb.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0)
self.platform.add_period_constraint(
self.platform.lookup_request("pcie_x1").clk_p, 10.0)
if with_analyzer:
analyzer_signals = [
self.pciephy.sink.valid, self.pciephy.sink.ready,
self.pciephy.sink.last, self.pciephy.sink.dat,
self.pciephy.sink.be, self.pciephy.source.valid,
self.pciephy.source.ready, self.pciephy.source.last,
self.pciephy.source.dat, self.pciephy.source.be
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
1024,
cd="sys")