def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check single level column mux in single port
debug.info(2, "Checking column mux")
tx = factory.create(module_type="single_level_column_mux", tx_size=8)
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check single level column mux array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(1,
"Testing sample for 2-way column_mux_array in multi-port")
a = factory.create(module_type="column_mux_array",
columns=16,
word_size=8,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(1,
"Testing sample for 4-way column_mux_array in multi-port")
a = factory.create(module_type="column_mux_array",
columns=16,
word_size=4,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(
1,
"Testing sample for 8-way column_mux_array in multi-port (innermost connections)"
)
a = factory.create(module_type="column_mux_array",
columns=32,
word_size=4,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(
1,
"Testing sample for 8-way column_mux_array in multi-port (outermost connections)"
)
a = factory.create(module_type="column_mux_array",
columns=32,
word_size=4,
bitcell_bl="bl2",
bitcell_br="br2",
column_offset=3)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ms_flop_array
debug.info(1, "Testing sample for dff_array")
OPTS.check_lvsdrc = False
a = ms_flop_array.ms_flop_array(
name="test1", array_type="address", columns=64, word_size=32)
OPTS.check_lvsdrc = True
self.local_check(a)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import nor_2
import tech
debug.info(2, "Checking 2-input nor gate")
tx = nor_2.nor_2(name="a_nor_1", nmos_width=2 * tech.drc["minwidth_tx"])
OPTS.check_lvsdrc = True
self.local_check(tx)
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.nominal_corner_only = False
OPTS.netlist_only = True
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank"
)
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
#Set the corners. Lib will create a power set of the lists.
if OPTS.tech_name == "scn4m_subm":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [5.0]
OPTS.temperatures = [25]
elif OPTS.tech_name == "freepdk45":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [1.0]
OPTS.temperatures = [25]
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.15))
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking min size NMOS with 1 finger")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import single_level_column_mux_array
debug.info(1, "Testing sample for columnmux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
rows=32, columns=32, word_size=16)
OPTS.check_lvsdrc = True
self.local_check(a)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = True
import ecc
debug.info(2, "Testing ECC for word_size=8")
dut = ecc.ecc(word_size=4)
self.local_check(dut)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
global verify
import verify
import pand3
debug.info(2, "Testing pand3 gate 4x")
a = pand3.pand3(name="pand3x4", size=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import control_logic
import tech
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128)
OPTS.check_lvsdrc = True
self.local_check(a)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
import pbuf
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pbuf.pbuf(name="pbufx8", size=8)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing dummy row for 6t_cell")
a = factory.create(module_type="dummy_array", rows=1, cols=4)
self.local_check(a)
debug.info(2, "Testing dummy column for 6t_cell")
a = factory.create(module_type="dummy_array", rows=4, cols=1)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking min size PMOS with 1 finger")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="pmos")
self.local_drc_check(fet)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import cell_multiport
import tech
debug.info(2, "Checking cell_multiport")
tx = cell_multiport.cell_multiport(name="cell_multiport", nmos_width=2 * tech.drc["minwidth_tx"])
OPTS.check_lvsdrc = True
self.local_check(tx)
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
# Doesn't require hierarchical decoder
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
# a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
# self.local_check(a)
# Doesn't require hierarchical decoder
# debug.info(1, "Testing 8 row sample for hierarchical_decoder")
# a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8)
# self.local_check(a)
# check hierarchical decoder for single port
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
# check hierarchical decoder for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import logic_effort_dc
debug.info(2, "Testing delay_chain")
a = logic_effort_dc.logic_effort_dc(
"chain", stage_list=[4, 4, 4, 4, 4])
OPTS.check_lvsdrc = True
self.local_check(a)
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
stages = 4
fanout = 4
rows = 13
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
factory.reset()
debug.info(
2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(
stages, rows))
a = factory.create(module_type="replica_bitline",
delay_fanout_list=stages * [fanout],
bitcell_loads=rows)
self.local_check(a)
# check replica bitline in pbitcell multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(
2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(
stages, rows))
a = factory.create(module_type="replica_bitline",
delay_fanout_list=stages * [fanout],
bitcell_loads=rows)
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
factory.reset()
debug.info(
2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".
format(stages, rows))
a = factory.create(module_type="replica_bitline",
delay_fanout_list=stages * [fanout],
bitcell_loads=rows)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_decoder
import tech
debug.info(1, "Testing 4 row sample for hierarchical_decoder")
OPTS.check_lvsdrc = False
a = hierarchical_decoder.hierarchical_decoder(
nand2_nmos_width=2 * tech.drc["minwidth_tx"],
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
rows=4)
OPTS.check_lvsdrc = True
self.local_check(a)
debug.info(1, "Testing 8 row sample for hierarchical_decoder")
OPTS.check_lvsdrc = False
a = hierarchical_decoder.hierarchical_decoder(
nand2_nmos_width=2 * tech.drc["minwidth_tx"],
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
rows=8)
OPTS.check_lvsdrc = True
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
OPTS.check_lvsdrc = False
a = hierarchical_decoder.hierarchical_decoder(
nand2_nmos_width=2 * tech.drc["minwidth_tx"],
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
rows=32)
OPTS.check_lvsdrc = True
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder")
OPTS.check_lvsdrc = False
a = hierarchical_decoder.hierarchical_decoder(
nand2_nmos_width=2 * tech.drc["minwidth_tx"],
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
rows=128)
OPTS.check_lvsdrc = True
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
OPTS.check_lvsdrc = False
a = hierarchical_decoder.hierarchical_decoder(
nand2_nmos_width=2 * tech.drc["minwidth_tx"],
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
rows=512)
OPTS.check_lvsdrc = True
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import pinv
# load the hspice
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
# generate the pinv
prev_keep_value = OPTS.keep_temp
# force set purge to false to save the sp file
OPTS.keep_temp = True
debug.info(2, "Checking 1x size inverter")
tx = pinv.pinv(name="pinv", size=1)
tempgds = "{}.gds".format(tx.name)
tx.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
tempsp = "{}.sp".format(tx.name)
tx.sp_write("{0}{1}".format(OPTS.openram_temp, tempsp))
# make sure that the library simulation is successful
sp_delay = self.simulate_delay(test_module=tempsp,
top_level_name=tx.name)
if sp_delay == "Failed":
self.fail('Library Spice module did not behave as expected')
# now generate its pex file
pex_file = self.run_pex(tx)
OPTS.keep_temp = prev_keep_value # restore the old keep
# generate simulation for pex, make sure the simulation is successful
pex_delay = self.simulate_delay(test_module=pex_file,
top_level_name=tx.name)
# make sure the extracted spice simulated
if pex_delay == "Failed":
self.fail('Pex file did not behave as expected')
# if pex data is bigger than original spice file then result is ok
# However this may not always be true depending on the netlist provided
# comment out for now
# debug.info(2,"pex_delay: {0}".format(pex_delay))
# debug.info(2,"sp_delay: {0}".format(sp_delay))
# assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\
# .format(pex_delay,sp_delay)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import setup_hold
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
import sram
import tech
slews = [tech.spice["rise_time"] * 2]
sh = setup_hold.setup_hold()
data = sh.analyze(slews, slews)
if OPTS.tech_name == "freepdk45":
golden_data = {
'setup_times_LH': [0.014648399999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0036620999999999997],
'setup_times_HL': [0.0085449]
}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {
'setup_times_LH': [0.1000977],
'hold_times_LH': [0.020751999999999996],
'hold_times_HL': [-0.0830078],
'setup_times_HL': [0.020751999999999996]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k]) == list:
for i in range(len(data[k])):
self.isclose(data[k][i], golden_data[k][i], 0.15)
else:
self.isclose(data[k], golden_data[k], 0.15)
OPTS.check_lvsdrc = True
OPTS.analytical_delay = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.")
out_file = "testsram"
# make a temp directory for output
out_path = "/tmp/testsram_{0}".format(OPTS.tech_name)
# make sure we start without the files existing
if os.path.exists(out_path):
shutil.rmtree(out_path, ignore_errors=True)
self.assertEqual(os.path.exists(out_path), False)
try:
os.makedirs(out_path, 0750)
except OSError as e:
if e.errno == 17: # errno.EEXIST
os.chmod(out_path, 0750)
# specify the same verbosity for the system call
verbosity = ""
for i in range(OPTS.debug_level):
verbosity += " -v"
OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
cmd = "python2.7 {0}/openram.py -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(
OPENRAM_HOME, out_file, out_path, verbosity, OPTS.tech_name,
out_path)
debug.info(1, cmd)
os.system(cmd)
# assert an error until we actually check a resul
for extension in ["gds", "v", "lef", "lib", "sp"]:
filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
debug.info(1, "Checking for file: " + filename)
self.assertEqual(os.path.exists(filename), True)
# grep any errors from the output
output = open("{0}/output.log".format(out_path), "r").read()
self.assertEqual(len(re.findall('ERROR', output)), 0)
self.assertEqual(len(re.findall('WARNING', output)), 0)
# now clean up the directory
if os.path.exists(out_path):
shutil.rmtree(out_path, ignore_errors=True)
self.assertEqual(os.path.exists(out_path), False)
# The default was on, so disable it.
OPTS.check_lvsdrc = False
globals.end_openram()
OPTS.check_lvsdrc = True
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import single_level_column_mux_array
debug.info(1, "Testing sample for 2-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=16, word_size=8)
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=16, word_size=4)
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=32, word_size=4)
self.local_check(a)
if OPTS.multiport_check:
debug.info(2, "Checking column mux array for pbitcell")
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
debug.info(1, "Testing sample for 2-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(
columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for 6t_cell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
left_rbl=1,
right_rbl=0,
bitcell_ports=[0])
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
import pand2
debug.info(2, "Testing pand2 gate 4x")
a = pand2.pand2(name="pand2x4", size=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
debug.info(2, "Checking min size NMOS with 1 finger")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import replica_bitline
debug.info(2, "Testing RBL")
a = replica_bitline.replica_bitline("chain", 13)
OPTS.check_lvsdrc = True
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16)
self.local_check(a)
debug.info(1, "Port address 512 rows")
a = factory.create("port_address", cols=256, rows=512)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(1, "Testing sample for control_logic_rw")
a = factory.create(module_type="control_logic",
num_rows=128,
words_per_row=1,
word_size=32)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver_array",
rows=8,
cols=32)
self.local_check(tx)
globals.end_openram()
