#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('shifter.py')
import sys
from myhdl import Signal, intbv, enum, always_seq, always_comb
from system import System
from wb import WbSlaveInterface
from clk import Clk
from rst import rstgen
from timebase import nsec
from regfile import RegFile, Port, Field, RoField, RwField, DummyField
from util import rename_interface
class ShifterBus(object):
def __init__(self, num_cs):
self.SCK = Signal(False)
self.SDO = Signal(False)
self.SDOE = Signal(False)
self.CS = Signal(intbv(0)[num_cs:])
class Shifter(object):
def __init__(self, system, bus, divider, width = 32, strict_sdoe = True):
self.system = system
self.bus = bus
self.states = enum(
"IDLE", "START", "PRE", "FIRST", "SECOND", "POST", "PULSE")
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_ddr.py')
from myhdl import Signal, ResetSignal, intbv, instance, delay, SignalType
from timebase import timescale, nsec, usec, msec, sec
from system import System
from ddr import Ddr, DdrBus, DdrSource, ddr_connect
from clk import Clk
from rst import rstgen
from util import rename_interface, mask
def setup(addr_depth = 1024, data_width = 16):
insts = []
clk = Clk(100E6)
insts.append(clk.gen())
if 1:
rst = ResetSignal(0, active = 1, async = 0)
insts.append(rstgen(rst, 100 * nsec, clk))
else:
rst = None
system = System(clk, rst)
bus = DdrBus(2, 12, 2)
rename_interface(bus, None)
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_wb.py')
from myhdl import Signal, ResetSignal, intbv, always, always_seq, always_comb
from wb import WbSlave, WbSyncSlave, WbMux
from ram import AsyncRam
def wb_write(bus, adr, dat, timeout=10):
print "wb_write", hex(adr), hex(dat), timeout
yield (bus.CLK_I.posedge)
bus.CYC_I.next = 1
bus.STB_I.next = 1
bus.WE_I.next = 1
bus.ADR_I.next = adr
bus.DAT_I.next = dat
for t in range(timeout):
yield (bus.CLK_I.posedge)
if bus.ACK_O:
print "write ACK", hex(bus.ADR_I), hex(bus.DAT_I)
break
elif bus.ERR_O:
print "write ERR", hex(bus.ADR_I), hex(bus.DAT_I)
break
elif bus.RTY_O:
print "write RTY", hex(bus.ADR_I), hex(bus.DAT_I)
else:
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('image.py')
from pprint import pprint
from myhdl import (Signal, TristateSignal, ConcatSignal,
intbv, always_comb, always_seq)
from rhea.cores.misc import syncro
from spartan6 import (startup_spartan6, bufg,
ibufds, ibufgds_diff_out, ibufds_vec, iddr2)
from system import System
from spi_slave import SpiInterface, SpiSlave
from wb import WbMux
from hybrid_counter import HybridCounter
from util import tristate
from regfile import RegFile, Field, RwField, Port
from ddr import Ddr, DdrBus, DdrSource, ddr_connect
from sampler import Sampler
from shifter import Shifter, ShifterBus
from ram import Ram
def top(din, init_b, cclk,
ref_clk,
soc_clk_p, soc_clk_n, soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
soc_dqs, soc_dm, soc_dq,
adc_clk_p, adc_clk_n, adc_dat_p, adc_dat_n, adc_ovr_p, adc_ovr_n,
shifter_sck, shifter_sdo,
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('wb.py')
from myhdl import Signal, SignalType, ResetSignal, intbv, always_seq, always_comb
class WbSlaveInterface(object):
def __init__(self, addr_depth, data_width):
addr_width = len(intbv(0, 0, addr_depth))
sel_width = (data_width + 7) / 8
self.CLK_I = Signal(False)
self.RST_I = ResetSignal(0, active = 1, async = 0)
self.CYC_I = Signal(False)
self.STB_I = Signal(False)
self.WE_I = Signal(False)
self.ACK_O = Signal(False)
self.ERR_O = Signal(False)
self.RTY_O = Signal(False)
self.ADR_I = Signal(intbv(0)[addr_width:])
self.SEL_I = Signal(intbv(~0)[sel_width:])
self.DAT_I = Signal(intbv(0)[data_width:])
self.DAT_O = Signal(intbv(0)[data_width:])
class WbBus(WbSlaveInterface):
def __init__(self, system, addr_depth, data_width):
super(WbBus, self).__init__(addr_depth, data_width)
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_spi_slave.py')
from myhdl import Signal, intbv, always_seq, always_comb
from ram import Ram
from spi_slave import SpiSlave, SpiInterface
from myhdl import instance, delay
def spi_test(bus, sclk_interval=43):
from myhdl import instance, delay
@instance
def logic():
yield delay(200)
bus.CS.next = 0
bus.SCK.next = 0
bus.SD_I.next = 0
yield delay(sclk_interval)
bus.CS.next = 1
yield delay(sclk_interval)
a = 0x1
print "Reg Write Addr", hex(int(a))
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_wb.py')
from myhdl import Signal, ResetSignal, intbv, always, always_seq, always_comb
from wb import WbSlave, WbSyncSlave, WbMux
from ram import AsyncRam
def wb_write(bus, adr, dat, timeout = 10):
print "wb_write", hex(adr), hex(dat), timeout
yield(bus.CLK_I.posedge)
bus.CYC_I.next = 1
bus.STB_I.next = 1
bus.WE_I.next = 1
bus.ADR_I.next = adr
bus.DAT_I.next = dat
for t in range(timeout):
yield(bus.CLK_I.posedge)
if bus.ACK_O:
print "write ACK", hex(bus.ADR_I), hex(bus.DAT_I)
break
elif bus.ERR_O:
print "write ERR", hex(bus.ADR_I), hex(bus.DAT_I)
break
elif bus.RTY_O:
print "write RTY", hex(bus.ADR_I), hex(bus.DAT_I)
else:
print "write timeout", hex(bus.ADR_I), hex(bus.DAT_I)
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_util.py')
from myhdl import ConcatSignal, SignalType, always_comb
def rename_interface(self, prefix):
for k, v in vars(self).items():
if isinstance(v, SignalType):
if prefix is None:
v._name = k
else:
v._name = prefix + '_' + k
def tristate(pin, i, o, oe):
driver = pin.driver()
@always_comb
def logic():
i.next = pin
if oe:
driver.next = o
else:
driver.next = None
return logic
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('ram.py')
from myhdl import Signal, intbv, always_seq, always_comb
from wb import WbSlave
class AsyncRam(WbSlave):
def __init__(self, addr_depth, data_width):
super(AsyncRam, self).__init__(addr_depth, data_width, async=True)
self.ram = [Signal(intbv(0)[data_width:]) for _ in range(addr_depth)]
def gen(self, bus):
@always_seq(bus.CLK_I.posedge, bus.RST_I)
def ram_write_inst():
if bus.CYC_I and bus.STB_I and bus.WE_I:
if bus.ADR_I < len(self.ram):
# When I try to synthesize the following with
# Xlinx ISE I get "h is not a constant"
# for sel in range(len(bus.SEL_I)):
# if bus.SEL_I[sel]:
# l = sel * 8
# h = sel * 8 + 8
# self.ram[bus.ADR_I].next[h:l] = bus.DAT_I[h:l]
self.ram[bus.ADR_I].next = bus.DAT_I
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('gray.py')
from myhdl import Signal, intbv, always, always_comb, instances
def gray_encode(bin_value):
return bin_value ^ (bin_value >> 1)
def gray_decode(gray_value):
bin_value = 0
t = 0
for i in range(len(gray_value)):
n = len(gray_value) - i - 1
t ^= gray_value[n]
bin_value |= t << n
return bin_value & ((1 << len(gray_value)) - 1)
def gray_encoder(bin_value, gray_value):
assert len(bin_value) == len(gray_value)
@always_comb
def comb():
gray_value.next = gray_encode(bin_value)
return comb
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('mig.py')
from myhdl import Signal, ResetSignal, SignalType, instance, always_comb, always_seq, intbv, instances
from simple.reg import Reg, Port, Field, RwField, RoField, DummyField
from spartan6 import pll_adv, bufg, bufgce, bufpll_mcb, mcb_ui_top
def mig_with_tb(sys_rst_i, sys_clk_p, sys_clk_n,
calib_done, error,
mcb3_dram_ck, mcb3_dram_ck_n,
mcb3_dram_ras_n, mcb3_dram_cas_n, mcb3_dram_we_n,
mcb3_dram_ba, mcb3_dram_a, mcb3_dram_odt,
mcb3_dram_dqs, mcb3_dram_dqs_n,
mcb3_dram_udqs, mcb3_dram_udqs_n,
mcb3_dram_dm, mcb3_dram_udm,
mcb3_dram_dq,
soc_clk, soc_clk_b = ''):
sys_rst_i.read = True
sys_clk_p.read = True
sys_clk_n.read = True
calib_done.driven = 'wire'
error.driven = 'wire'
mcb3_dram_ck.driven = 'wire'
mcb3_dram_ck_n.driven = 'wire'
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('ram.py')
from myhdl import Signal, intbv, always_seq, always_comb
from wb import WbSlave
class AsyncRam(WbSlave):
def __init__(self, addr_depth, data_width):
super(AsyncRam, self).__init__(addr_depth, data_width, async = True)
self.ram = [ Signal(intbv(0)[data_width:]) for _ in range(addr_depth) ]
def gen(self, bus):
@always_seq(bus.CLK_I.posedge, bus.RST_I)
def ram_write_inst():
if bus.CYC_I and bus.STB_I and bus.WE_I:
if bus.ADR_I < len(self.ram):
# When I try to synthesize the following with
# Xlinx ISE I get "h is not a constant"
# for sel in range(len(bus.SEL_I)):
# if bus.SEL_I[sel]:
# l = sel * 8
# h = sel * 8 + 8
# self.ram[bus.ADR_I].next[h:l] = bus.DAT_I[h:l]
self.ram[bus.ADR_I].next = bus.DAT_I
@always_comb
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('ddr.py')
from myhdl import Signal, intbv, always, always_seq, always_comb
from util import mask, lsh
class DdrBus(object):
def __init__(self, ba_width, a_width, d_width):
self.ba_width = ba_width
self.a_width = a_width
self.d_width = d_width
self.CS_B = Signal(True)
self.RAS_B = Signal(True)
self.CAS_B = Signal(True)
self.WE_B = Signal(True)
self.BA = Signal(intbv(~0)[ba_width:])
self.A = Signal(intbv(~0)[a_width:])
self.DQS0_O = Signal(intbv(0)[d_width:])
self.DQS0_I = Signal(intbv(0)[d_width:])
self.DQS0_OE = Signal(False)
self.DM0_I = Signal(intbv(0)[d_width:])
self.DM0_O = Signal(intbv(0)[d_width:])
self.DM0_OE = Signal(intbv(0)[d_width:])
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_util.py')
from myhdl import Signal, intbv, always
from clk import Clk
from util import Packer
class Interface(object):
def __init__(self, n):
self.a = Signal(False)
self.b = Signal(intbv(0)[n:])
self.c = Signal(False)
def test(clk):
insts = []
p = Packer(Interface, 3)
src = p.create()
packed = p.pack(src)
dst = p.create()
unpack_inst = p.unpack(packed, dst)
insts.append(unpack_inst)
@always (clk)
def test_inst():
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('sampler.py')
from myhdl import Signal, intbv, always, always_seq, always_comb
from wb import WbSlave
class Sampler(WbSlave):
def __init__(self, addr_depth, sample_clk, sample_data, sample_enable,
skip_cnt = 0):
data_width = len(sample_data)
super(Sampler, self).__init__(addr_depth, data_width, async = True)
self.ram = [ Signal(intbv(0)[data_width:]) for _ in range(addr_depth) ]
self.sample_clk = sample_clk
self.sample_data = sample_data
self.sample_enable = sample_enable
self.skip_cnt = skip_cnt
def gen(self, bus):
req = Signal(False)
@always_comb
def comb():
req.next = (bus.CYC_I and bus.STB_I and
not bus.ACK_O and not bus.ERR_O and not bus.RTY_O)
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('hybrid_counter.py')
from myhdl import Signal, intbv, always_comb, always_seq
from gray import gray_decoder, gray_counter
from wb import WbSlave
class HybridCounter(WbSlave):
"""A hybrid asynchronous/synchronous counter which can count
higher frequencies than sysclk on a number of pins.
An asynchronous gray counter which counts the number of positive
edges on a set of pins. Each counter is split into an
asynchronous part that can run faster than sysclk and a
synchronous part that is updated periodically.
The purpose of this counter is to save on the number of ripple
carry resources used in an FPGA and to let the asynchronous
counters run faster than they could have done otherwise. It's
only possible to fit about 80 asynchronous 32 bit counters into a
Xilinx XC6SLX9 FPGA before the it runs out of space. With the
hybrid approach where only the lower 12 bits are updated
asynchronously should be able to fit two or three times as many
counters into the same FPGA.
An asynchronous gray counter increments the lower async_width of
the counter on every positive edge of the pin.
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('gray.py')
from myhdl import Signal, intbv, always, always_comb, instances
def gray_encode(bin_value):
return bin_value ^ (bin_value >> 1)
def gray_decode(gray_value):
bin_value = 0
t = 0
for i in range(len(gray_value)):
n = len(gray_value) - i - 1
t ^= gray_value[n]
bin_value |= t << n
return bin_value & ((1<<len(gray_value)) - 1)
def gray_encoder(bin_value, gray_value):
assert len(bin_value) == len(gray_value)
@always_comb
def comb():
gray_value.next = gray_encode(bin_value)
return comb
def gray_decoder(gray_value, bin_value):
assert len(gray_value) == len(bin_value)
@always_comb
def comb():
bin_value.next = gray_decode(gray_value)
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_spi_slave.py')
from myhdl import Signal, intbv, always_seq, always_comb
from ram import Ram
from spi_slave import SpiSlave, SpiInterface
from myhdl import instance, delay
def spi_test(bus, sclk_interval = 43):
from myhdl import instance, delay
@instance
def logic():
yield delay(200)
bus.CS.next = 0
bus.SCK.next = 0
bus.SD_I.next = 0
yield delay(sclk_interval)
bus.CS.next = 1
yield delay(sclk_interval)
a = 0x1
print "Reg Write Addr", hex(int(a))
dd = a << 1
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('test_mux.py')
from myhdl import Signal, intbv, always_comb, always_seq
from bus import Bus
class Mux(object):
def __init__(self, system):
self.system = system
self.slaves = []
self.addr = 0
self.align = True
self.pad = True
self.addr = 0
self.addr_depth = 0
self.data_width = 0
self._bus = None
def bus(self):
if self._bus is None:
self._bus = Bus(self.addr_depth, self.data_width)
return self._bus
def add(self, slaves, addr = None, align = None, pad = None):
if isinstance(slaves, Bus):
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('memory.py')
from pprint import pprint
from myhdl import (Signal, TristateSignal, ConcatSignal,
intbv, always_comb, always_seq)
from rhea.cores.misc import syncro
from spartan6 import (startup_spartan6, bufg,
ibufds, ibufgds_diff_out, ibufds_vec, iddr2)
from system import System
from spi_slave import SpiInterface, SpiSlave
from wb import WbMux
from hybrid_counter import HybridCounter
from util import tristate
from regfile import RegFile, Field, RoField, RwField, Port
from ddr import Ddr, DdrBus, DdrSource, ddr_connect
from sampler import Sampler
from shifter import Shifter, ShifterBus
from ram import Ram
from mig import mig
def top(din, init_b, cclk,
ref_clk,
soc_clk_p, soc_clk_n, soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
soc_dqs, soc_dm, soc_dq,
adc_clk_p, adc_clk_n, adc_dat_p, adc_dat_n, adc_ovr_p, adc_ovr_n,
#! /usr/bin/python
import hacking
if __name__ == '__main__':
hacking.reexec_if_needed('regfile.py')
from myhdl import Signal, SignalType, always_comb, always_seq, intbv
from timebase import sec
from util import rename_interface
from wb import WbSlave
class Port(object):
def __init__(self, value):
self.STB = Signal(False)
self.WE = Signal(False)
self.DAT_I = Signal(value)
self.DAT_O = Signal(value)
class Field(object):
def __init__(self, system, name, description, port):
self.system = system
self.name = name
self.description = description
self.port = port
def gen(self, bus):
@always_comb
def comb():
self.port.STB.next = bus.STB_I
self.port.WE.next = bus.WE_I
self.port.DAT_I.next = bus.DAT_I[self.offset+self.width:self.offset]
bus.DAT_O.next[self.offset+self.width:self.offset] = self.port.DAT_O