def convert():
"""
Convert the myHDL design into VHDL and Verilog
:return:
"""
wsi = Signal(bool(0))
wsp_inst = wsp()
select_wir = Signal(bool(1))
wso = Signal(bool(0))
wr_list = ['WS_BYPASS', 'WS_EXTEST', 'WS_INTEST']
user_list = ['MBIST1', 'MBIST2', 'MBIST3']
wr_select_list = Signal(intbv(0)[len(wr_list):])
dr_select_list = Signal(intbv(0)[len(user_list):])
wir_inst = wir('TOP',
'WIR0',
wsi,
wsp_inst,
wso,
wr_list,
user_list,
wr_select_list,
dr_select_list,
monitor=False)
vhdl_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'vhdl')
if not os.path.exists(vhdl_dir):
os.mkdir(vhdl_dir, mode=0o777)
wir_inst.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="wir")
verilog_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)),
'verilog')
if not os.path.exists(verilog_dir):
os.mkdir(verilog_dir, mode=0o777)
wir_inst.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="wir")
tb = wir_tb(monitor=False)
tb.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="wir_tb")
tb.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="wir_tb")
def convert():
"""
Convert the myHDL design into VHDL and Verilog
:return:
"""
dr_width = 9
si = Signal(bool(0))
so = Signal(bool(0))
di = Signal(intbv('000000000')[dr_width:])
do = Signal(intbv(0)[dr_width:])
wsp_interface = wsp()
dr_select = Signal(bool(1))
wsreg_inst = WSReg('TOP',
'SReg0',
si,
wsp_interface,
dr_select,
so,
di,
do,
dr_width=9,
monitor=False)
vhdl_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'vhdl')
if not os.path.exists(vhdl_dir):
os.mkdir(vhdl_dir, mode=0o777)
wsreg_inst.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="SReg")
verilog_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)),
'verilog')
if not os.path.exists(verilog_dir):
os.mkdir(verilog_dir, mode=0o777)
wsreg_inst.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="SReg")
tb = WSReg_tb(monitor=False)
tb.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="SReg_tb")
tb.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="SReg_tb")
def convert():
"""
Convert the myHDL design into VHDL and Verilog
:return:
"""
width = 1
wsi = Signal(bool(0))
wby_wso = Signal(bool(0))
select = Signal(bool(1))
wsp_interface_inst = wsp()
wsp_interface_inst.SelectWIR = Signal(bool(0))
wby_inst = wby("DEMO",
"WBY0",
wsi,
wsp_interface_inst,
select,
wby_wso,
width=width,
monitor=False)
vhdl_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'vhdl')
if not os.path.exists(vhdl_dir):
os.mkdir(vhdl_dir, mode=0o777)
wby_inst.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="wby")
verilog_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)),
'verilog')
if not os.path.exists(verilog_dir):
os.mkdir(verilog_dir, mode=0o777)
wby_inst.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="wby")
tb = wby_tb(monitor=False)
tb.convert(hdl="VHDL",
initial_values=True,
directory=vhdl_dir,
name="wby_tb")
tb.convert(hdl="Verilog",
initial_values=True,
directory=verilog_dir,
name="wby_tb")
def wby_tb(monitor=False):
"""
Test bench interface for a quick test of the operation of the design
:param monitor: False=Do not turn on the signal monitors, True=Turn on the signal monitors
:return: A list of generators for this logic
"""
hi = bool(1)
lo = bool(0)
width = 1
# data = [hi, lo, hi, hi, lo]
data = Signal(intbv('01101'))
ldata = 5
# expect = [lo, hi, lo, hi, hi, lo]
expect = Signal(intbv('011010'))
wsi = Signal(bool(0))
wby_wso = Signal(bool(0))
select = Signal(bool(0))
wsp_interface_inst = wsp()
wby_inst = wby("DEMO",
"WBY0",
wsi,
wsp_interface_inst,
select,
wby_wso,
width=width,
monitor=monitor)
@instance
def clkgen():
while True:
wsp_interface_inst.WRCK.next = not wsp_interface_inst.WRCK
yield delay(period // 2)
# print simulation data to file
file_data = open("wby_tb.csv", 'w') # file for saving data
# print header to file
print("{0},{1},{2},{3},{4},{5},{6}".format("wsi", "CaptureWR", "ShiftWR",
"UpdateWR", "SelectWIR",
"select", "wby_wso"),
file=file_data)
# print data on each tap_interface.ClockDR
@always(wsp_interface_inst.WRCK.posedge)
def print_data():
"""
"""
# print in file
# print.format is not supported in MyHDL 1.0
print(wsi,
",",
wsp_interface_inst.CaptureWR,
",",
wsp_interface_inst.ShiftWR,
",",
wsp_interface_inst.UpdateWR,
",",
wsp_interface_inst.SelectWIR,
",",
select,
",",
wby_wso,
file=file_data)
@instance
def stimulus():
"""
Not true IJTAG protocol, but used to exercise the state machine with the fewest cycles
:return:
"""
# Reset the instrument
wsp_interface_inst.WRSTN.next = lo
yield delay(10)
wsp_interface_inst.WRSTN.next = hi
yield delay(10)
# Capture Value of bool(0)
select.next = hi
wsp_interface_inst.CaptureWR.next = hi
yield wsp_interface_inst.WRCK.negedge
yield wsp_interface_inst.WRCK.posedge
# Write Shift value
wsp_interface_inst.CaptureWR.next = lo
wsp_interface_inst.ShiftWR.next = hi
yield wsp_interface_inst.WRCK.negedge
for i in range(ldata):
wsi.next = data[i]
yield wsp_interface_inst.WRCK.posedge
yield wsp_interface_inst.WRCK.negedge
assert (wby_wso == expect[i])
wsi.next = lo
yield wsp_interface_inst.WRCK.posedge
yield wsp_interface_inst.WRCK.negedge
assert (wby_wso == expect[len(data)])
yield delay(100)
raise StopSimulation()
return wby_inst, clkgen, stimulus, print_data
def WSReg_tb(monitor=False):
"""
Test bench interface for a quick test of the operation of the design
:param monitor: False=Do not turn on the signal monitors, True=Turn on the signal monitors
:return: A list of generators for this logic
"""
dr_width = 9
si = Signal(bool(0))
so = Signal(bool(0))
di = Signal(intbv('010100000')[dr_width:])
do = Signal(intbv(0)[dr_width:])
si_data = Signal(intbv('000000101')[dr_width:])
so_data = [Signal(bool(0)) for _ in range(dr_width)]
wsp_interface = wsp()
dr_select = Signal(bool(1))
wsreg_inst = WSReg('TOP',
'WSReg0',
si,
wsp_interface,
dr_select,
so,
di,
do,
dr_width=dr_width,
monitor=monitor)
@instance
def clkgen():
while True:
wsp_interface.WRCK.next = not wsp_interface.WRCK
yield delay(period // 2)
# print simulation data to file
file_data = open("WSReg_tb.csv", 'w') # file for saving data
# print header to file
print("{0},{1},{2},{3},{4},{5},{6},{7}".format("si", "ce", "se", "ue",
"sel", "so", "di", "do"),
file=file_data)
# print data on each tap_interface.ClockDR
@always(wsp_interface.WRCK.posedge)
def print_data():
"""
"""
# print in file
# print.format is not supported in MyHDL 1.0
print(si,
",",
wsp_interface.CaptureWR,
",",
wsp_interface.ShiftWR,
",",
wsp_interface.UpdateWR,
",",
wsp_interface.SelectWIR,
",",
so,
",",
di,
",",
do,
file=file_data)
@instance
def stimulus():
"""
Not true IJTAG protocol, but used to exercise the state machine with the fewest cycles
:return:
"""
H = bool(1)
L = bool(0)
# Reset the instrument
wsp_interface.WRSTN.next = bool(0)
yield delay(10)
wsp_interface.WRSTN.next = bool(1)
yield delay(10)
# Start the Capture transition operation
yield wsp_interface.WRCK.posedge
# Write Capture value
wsp_interface.CaptureWR.next = H
yield wsp_interface.WRCK.negedge
yield wsp_interface.WRCK.posedge
# Write Shift value
wsp_interface.CaptureWR.next = L
wsp_interface.ShiftWR.next = H
yield wsp_interface.WRCK.negedge
for i in range(dr_width):
si.next = si_data[i]
yield wsp_interface.WRCK.posedge
yield wsp_interface.WRCK.negedge
print("so = ", so)
so_data[i].next = so
# Write Update value
wsp_interface.ShiftWR.next = L
wsp_interface.UpdateWR.next = H
yield wsp_interface.WRCK.negedge
yield wsp_interface.WRCK.posedge
j = dr_width - 1
print("so_data = ", so_data)
while j > -1:
print("so_data[", j, "] = ", so_data[j])
if j == 5 or j == 7:
assert (so_data[j] == bool(1))
else:
assert (so_data[j] == bool(0))
j = j - 1
print("do = ", do)
for j in range(dr_width):
print("do[", j, "] = ", do[j])
if j == 0 or j == 2:
assert (do[j] == bool(1))
else:
assert (do[j] == bool(0))
assert (do == intbv('000000101'))
raise StopSimulation()
return wsreg_inst, clkgen, stimulus, print_data
def wir_tb(monitor=False):
"""
Test bench interface for a quick test of the operation of the design
:param monitor: False=Do not turn on the signal monitors, True=Turn on the signal monitors
:return: A list of generators for this logic
"""
H = bool(1)
L = bool(0)
wsi = Signal(bool(0))
wsp_inst = wsp()
wsp_inst.SelectWIR = Signal(bool(1))
wso = Signal(bool(0))
wr_list = ['WS_BYPASS', 'WS_EXTEST', 'WS_INTEST']
user_list = ['MBIST1', 'MBIST2', 'MBIST3']
wr_select_list = Signal(intbv(0)[len(wr_list):])
dr_select_list = Signal(intbv(0)[len(user_list):])
# ws_bypass = [L, L, L]
# ws_extest = [H, L, L]
# ws_intest = [L, H, L]
# mbist1 = [H, H, L]
# mbist2 = [L, L, H]
# mbist3 = [H, L, H]
ws_bypass = [Signal(bool(0)), Signal(bool(0)), Signal(bool(0))]
ws_extest = [Signal(bool(1)), Signal(bool(0)), Signal(bool(0))]
ws_intest = [Signal(bool(0)), Signal(bool(1)), Signal(bool(0))]
mbist1 = [Signal(bool(1)), Signal(bool(1)), Signal(bool(0))]
mbist2 = [Signal(bool(0)), Signal(bool(0)), Signal(bool(1))]
mbist3 = [Signal(bool(1)), Signal(bool(0)), Signal(bool(1))]
width = len(bin(intbv(0, min=0, max=(len(wr_list) + len(user_list))).max))
wir_inst = wir('TOP',
'WIR0',
wsi,
wsp_inst,
wso,
wr_list,
user_list,
wr_select_list,
dr_select_list,
monitor=monitor)
@instance
def clkgen():
while True:
wsp_inst.WRCK.next = not wsp_inst.WRCK
yield delay(period // 2)
# print simulation data to file
file_data = open("wir_tb.csv", 'w') # file for saving data
# print header to file
print("{0},{1},{2},{3},{4},{5}".format("wsi", "CaptureWR", "ShiftWR",
"UpdateWR", "SelectWIR", "wso"),
file=file_data)
# print data on each tap_interface.ClockDR
@always(wsp_inst.WRCK.posedge)
def print_data():
"""
"""
# print in file
# print.format is not supported in MyHDL 1.0
print(wsi,
",",
wsp_inst.CaptureWR,
",",
wsp_inst.ShiftWR,
",",
wsp_inst.UpdateWR,
",",
wsp_inst.SelectWIR,
",",
wso,
file=file_data)
@instance
def stimulus():
"""
Perform instruction decoding for various instructions
:return:
"""
# Reset the WIR
wsp_inst.WRSTN.next = bool(0)
yield delay(10)
wsp_inst.WRSTN.next = bool(1)
yield delay(10)
# Start with WS_BYPASS instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
print("width = ", width)
for i in range(width):
wsi.next = ws_bypass[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == ws_bypass[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == H) # WS_BYPASS selected
assert (wr_select_list[1] == L) # WS_EXTEST deselected
assert (wr_select_list[2] == L) # WS_INTEST deselected
for i in range(1, len(dr_select_list)):
assert (dr_select_list[i] == L)
# Start with WS_EXTEST instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
for i in range(width):
wsi.next = ws_extest[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == ws_bypass[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == L) # WS_BYPASS deselected
assert (wr_select_list[1] == H) # WS_EXTEST selected
assert (wr_select_list[2] == L) # WS_INTEST deselected
for i in range(1, len(dr_select_list)):
assert (dr_select_list[i] == L)
# Start with WS_INTEST instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
for i in range(width):
wsi.next = ws_intest[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == ws_extest[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == L) # WS_BYPASS deselected
assert (wr_select_list[1] == L) # WS_EXTEST deselected
assert (wr_select_list[2] == H) # WS_INTEST selected
for i in range(1, len(dr_select_list)):
assert (dr_select_list[i] == L)
# Start with MBIST1 instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
for i in range(width):
wsi.next = mbist1[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == ws_intest[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == L) # WS_BYPASS deselected
assert (wr_select_list[1] == L) # WS_EXTEST deselected
assert (wr_select_list[2] == L) # WS_INTEST deselected
assert (dr_select_list[0] == H) # MBIST1 selected
assert (dr_select_list[1] == L) # MBIST2 deselected
assert (dr_select_list[2] == L) # MBIST3 deselected
# Start with MBIST2 instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
for i in range(width):
wsi.next = mbist2[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == mbist1[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == L) # WS_BYPASS deselected
assert (wr_select_list[1] == L) # WS_EXTEST deselected
assert (wr_select_list[2] == L) # WS_INTEST deselected
assert (dr_select_list[0] == L) # MBIST1 deselected
assert (dr_select_list[1] == H) # MBIST2 selected
assert (dr_select_list[2] == L) # MBIST3 deselected
# Start with MBIST3 instruction
# Start the Capture transition operation
yield wsp_inst.WRCK.posedge
# Write Capture value
wsp_inst.CaptureWR.next = H
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
# Write Shift value
wsp_inst.CaptureWR.next = L
wsp_inst.ShiftWR.next = H
yield wsp_inst.WRCK.negedge
for i in range(width):
wsi.next = mbist3[i]
yield wsp_inst.WRCK.posedge
yield wsp_inst.WRCK.negedge
assert (wso == mbist2[i])
# Write Update value
wsp_inst.ShiftWR.next = L
wsp_inst.UpdateWR.next = H
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
wsp_inst.UpdateWR.next = L
yield wsp_inst.WRCK.negedge
yield wsp_inst.WRCK.posedge
assert (wr_select_list[0] == L) # WS_BwspYPASS deselected
assert (wr_select_list[1] == L) # WS_EXTEST deselected
assert (wr_select_list[2] == L) # WS_INTEST deselected
assert (dr_select_list[0] == L) # MBIST1 deselected
assert (dr_select_list[1] == L) # MBIST2 deselected
assert (dr_select_list[2] == H) # MBIST3 selected
raise StopSimulation()
return wir_inst, clkgen, stimulus, print_data