def test_parser_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
c.parse(None, "bad", None)
e = str(context.exception)
self.assertIn(
"'bad' is not recognized (expected hdlConvertor.language.Language value)", e)
def test(self):
c = HdlConvertor()
incdirs = []
c.parse([
sv_file,
],
Language.SYSTEM_VERILOG_2017,
incdirs,
debug=False)
def test_parser_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
test_result = c.parse(None, Language.SYSTEM_VERILOG_2012, None)
e = str(context.exception)
self.assertIn(
"Language.SYSTEM_VERILOG_2012 is not recognized (expected verilog, vhdl or systemVerilog",
e)
def test(self):
c = HdlConvertor()
c.preproc_macro_db.update(test_spec.preproc_defs)
try:
c.parse([test_spec.main_file, ], test_spec.language,
test_spec.include_dirs, debug=test_spec.debug)
except Exception:
if test_spec.should_fail:
# [TODO] some expected erros in this test suite are not related to synatax
# need to check maually if the error really means syntax error and
# if this library is raising it correctly
pass
else:
raise
test_filter.mark_test_as_passed(self)
def parseFile(fname, language, input_dir=None):
input_dir = get_language_path(input_dir, language)
inc_dir = path.join(TEST_DIR, input_dir)
f = path.join(TEST_DIR, input_dir, fname)
c = HdlConvertor()
res = c.parse([
f,
], language, [inc_dir], debug=True)
return f, res
def parseFile(fname, language):
_language = language
if language == SV:
_language = VERILOG
inc_dir = path.join(TEST_DIR, _language.value)
f = path.join(BASE_DIR, "tests", _language.value, fname)
c = HdlConvertor()
res = c.parse([f, ], language, [inc_dir], debug=True)
return f, res
def test_multiple_files_at_once(self):
language = VERILOG
f = [path.join(TEST_DIR, language.value, f)
for f in ["fifo_rx.v", "define.v", "arbiter.v", "uart.v"]]
inc_dir = path.join(TEST_DIR, language.value)
c = HdlConvertor()
res = c.parse(f, language, [inc_dir], debug=True)
e = [ o for o in res.objs if isinstance(o, HdlModuleDef)]
self.assertSetEqual(set(_e.module_name for _e in e),
{'fifo_rx', 'test', 'arbiter', 'uart'})
str(res)
def parseFile(fname, language):
if language.is_system_verilog():
lang_dir = os.path.join("sv_test", "others")
elif language.is_verilog():
lang_dir = "verilog"
elif language.is_vhdl():
lang_dir = "vhdl"
else:
raise ValueError(language)
inc_dir = path.join(TEST_DIR, lang_dir)
f = path.join(TEST_DIR, lang_dir, fname)
c = HdlConvertor()
res = c.parse([
f,
], language, [inc_dir], debug=True)
return f, res
and o.module_name == last.name, (last, o)
self.print_module_body(o)
else:
raise NotImplementedError(o)
last = o
if __name__ == "__main__":
import os
import sys
BASE_DIR = os.path.join(os.path.dirname(__file__), "..")
TEST_DIR = os.path.join(BASE_DIR, 'tests', 'verilog')
from hdlConvertor.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
filenames = [os.path.join(TEST_DIR, "arbiter_tb.v")]
#AES = os.path.join(BASE_DIR, "..", "aes")
#files = [
# # "aes_cipher_top.v",
# # "aes_key_expand_128.v",
# # "aes_inv_cipher_top.v", "aes_rcon.v",
# "test_bench_top.v",
# # "aes_inv_sbox.v", "aes_sbox.v",
#]
#
#filenames = [os.path.join(AES, f) for f in files]
d = c.parse(filenames, Language.VERILOG, [], False, True)
tv = ToVerilog(sys.stdout)
tv.print_context(d)
"""
:type context: HdlContext
"""
w = self.out.write
for o in context.objs:
if isinstance(o, HdlModuleDec):
w("\n")
self.print_module_header(o)
w("\n")
elif isinstance(o, HdlModuleDef):
self.print_module_body(o)
elif isinstance(o, HdlImport):
self.print_hdl_import(o)
else:
raise NotImplementedError(o)
if __name__ == "__main__":
import os
import sys
BASE_DIR = os.path.join(os.path.dirname(__file__), "..")
TEST_DIR = os.path.join(BASE_DIR, 'tests', 'vhdl')
from hdlConvertor.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
filenames = [os.path.join(TEST_DIR, "mux.vhd")]
d = c.parse(filenames, Language.VHDL, [], False, False)
tv = ToVhdl(sys.stdout)
tv.print_context(d)
"""
last = None
for o in context.objs:
if isinstance(o, HdlModuleDec):
self.print_module_header(o)
elif isinstance(o, HdlModuleDef):
assert isinstance(last, HdlModuleDec) \
and o.module_name == last.name, (last, o)
self.print_module_body(o)
else:
raise NotImplementedError(o)
last = o
if __name__ == "__main__":
import os
import sys
BASE_DIR = os.path.join(os.path.dirname(__file__), "..")
TEST_DIR = os.path.join(BASE_DIR, 'tests', 'verilog')
from hdlConvertor.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
# filenames = [os.path.join(TEST_DIR, "sram.v")]
filenames = [os.path.join(TEST_DIR, "aes.v")]
d = c.parse(filenames, Language.VERILOG, [
TEST_DIR,
], False, True)
tv = ToVerilog(sys.stdout)
tv.print_context(d)
def main(std_ver, include_dirs, files):
c = HdlConvertor()
# c.preproc_macro_db.update(preproc_defs)
if include_dirs is None:
include_dirs = []
c.parse(files, std_ver, include_dirs)
import sys
import traceback
from collections import namedtuple
from hdlConvertor import HdlConvertor
from hdlConvertor.hdlAst import HdlModuleDef, HdlStmAssign, HdlCall
from hdlConvertor.language import Language
from hdlConvertor.toVhdl import ToVhdl
from circuits import DipCircuitLayoutSpec, BufferCircuitLayoutSpec, DFlipFlopCircuitLayoutSpec, CircuitSpec, SimCircuit, \
temp_name_generator
c = HdlConvertor()
filenames = ["vhdl/mux.vhd", ]
include_dirs = []
d = c.parse(filenames, Language.VHDL, include_dirs, hierarchyOnly=False, debug=True)
def flatten_visitor(node, name_gen, root_children):
assert isinstance(node, HdlStmAssign)
if isinstance(node.src, HdlCall):
for i, op in enumerate(node.src.ops):
if isinstance(op, HdlCall):
t = next(name_gen)
gen_assign = HdlStmAssign(op, t)
flatten_visitor(gen_assign, name_gen, root_children)
node.src.ops[i] = t