def visit_HdlStmIf(self, o):
return method_as_function(ToVerilog2005Stm.visit_HdlStmIf)(self, o)
def visit_HdlStmContinue(self, o):
return method_as_function(ToVerilog2005Stm.visit_HdlStmContinue)(self,
o)
def visit_HdlModuleDef(self, mod_def):
"""
:type mod_def: HdlModuleDef
"""
mod_dec = mod_def.dec
assert mod_dec is not None, mod_def
assert not mod_dec.objs, mod_dec
w = self.out.write
if self.add_imports:
w(DEFAULT_IMPORTS)
w("\n")
if self.module_path_prefix is None:
self.add_imports = False
split_HdlModuleDefObjs = method_as_function(ToBasicHdlSimModel.split_HdlModuleDefObjs)
otherDefs, variables, processes, components = \
split_HdlModuleDefObjs(self, mod_def.objs)
method_as_function(ToBasicHdlSimModel.visit_component_imports)(self, components)
w("class ")
w(mod_dec.name)
w("(Unit):\n")
with Indent(self.out):
self.visit_doc(mod_dec, doc_string=True)
params_names = []
if mod_dec.params:
w('def _config(self):\n')
with Indent(self.out):
try:
self._is_param = True
for p in mod_dec.params:
self.visit_HdlIdDef(p, None)
params_names.append(p.name)
finally:
self._is_param = False
w("\n")
types = []
for d in otherDefs:
if isinstance(d, HdlFunctionDef):
self.visit_HdlFunctionDef(d)
elif isinstance(d, iHdlTypeDef):
types.append(d)
else:
raise NotImplementedError(d)
names_of_constants = set(params_names)
port_params_comp_names = [*params_names]
w('def _declr(self):\n')
with Indent(self.out):
self.ivars_to_local_vars(port_params_comp_names)
for t in types:
self.visit_type_declr(t)
w('# ports\n')
try:
self._is_port = True
for p in mod_dec.ports:
self.visit_HdlIdDef(p, names_of_constants)
port_params_comp_names.append(p.name)
finally:
self._is_port = False
w("# component instances\n")
for c in components:
if c.param_map:
w(c.name.val)
w(" = ")
w("self.")
w(c.name.val)
w(" = ")
w(c.module_name.val)
w('()\n')
port_params_comp_names.append(c.name.val)
for cp in c.param_map:
mod_p, val = pop_port_or_param_map(cp)
w(c.name.val)
w(".")
w(mod_p.val)
w(" = ")
self.visit_iHdlExpr(val)
w("\n")
w("\n")
w("def _impl(self):\n")
with Indent(self.out):
self.ivars_to_local_vars(port_params_comp_names)
w("# internal signals\n")
for v in variables:
self.visit_HdlIdDef(v, names_of_constants)
for c in components:
for pm in c.port_map:
mod_port, connected_sig = pop_port_or_param_map(pm)
assert isinstance(
connected_sig, HdlValueId), connected_sig
p = mod_port.obj
assert p is not None, (
"HdlValueId to module ports "
"shoudl have been discovered before")
d = p.direction
assert d.name in (HdlDirection.IN.name,
HdlDirection.OUT.name), d
is_input = d.name == HdlDirection.IN.name
if is_input:
w(c.name.val)
w(".")
self.visit_iHdlExpr(mod_port)
w("(")
self.visit_iHdlExpr(connected_sig)
w(")\n")
else:
self.visit_iHdlExpr(connected_sig)
w("(")
w(c.name.val)
w(".")
self.visit_iHdlExpr(mod_port)
w(")\n")
for p in processes:
self.visit_iHdlStatement(p)
# extra line to separate a process functions
w("\n")
def visit_iHdlStatement_in_statement(self, stm):
return method_as_function(
ToVerilog2005Stm.visit_iHdlStatement_in_statement)(self, stm)
def visit_HdlModuleDef(self, mod_def):
"""
:type mod_def: HdlModuleDef
"""
mod_dec = mod_def.dec
assert mod_dec is not None, mod_def
assert not mod_dec.objs, mod_dec
w = self.out.write
w(DEFAULT_IMPORTS)
w("\n")
split_HdlModuleDefObjs = method_as_function(
ToBasicHdlSimModel.split_HdlModuleDefObjs)
types, variables, processes, components = \
split_HdlModuleDefObjs(self, mod_def.objs)
self.visit_doc(mod_dec)
method_as_function(ToBasicHdlSimModel.visit_component_imports)(
self, components)
w("SC_MODULE(")
w(mod_dec.name)
w(") {\n")
with Indent(self.out):
if mod_dec.params:
raise NotImplementedError()
for t in types:
self.visit_type_declr(t)
w(";\n")
w('// ports\n')
try:
self._is_port = True
for p in mod_dec.ports:
self.visit_HdlIdDef(p)
w(";\n")
finally:
self._is_port = False
w("// component instances\n")
for c in components:
w(c.module_name.val)
w(" ")
w(c.name.val)
w('();\n')
w("// internal signals\n")
for v in variables:
self.visit_HdlIdDef(v)
w(";\n")
for p in processes:
self.visit_iHdlStatement(p)
# extra line to separate a process functions
w("\n")
w("SC_CTOR(")
w(mod_dec.name)
w(")")
if components:
w(": ")
for last, c in iter_with_last(components):
w(c.name.val)
w('("')
w(c.name.val)
if last:
w('")')
else:
w('"), ')
w(" {\n")
with Indent(self.out):
for p in processes:
if p.sensitivity:
w("SC_METHOD(")
w(p.labels[0])
w(");\n")
w("sensitive")
for s in p.sensitivity:
w(" << ")
self.visit_iHdlExpr(s)
w(";\n")
else:
w(p.labels[0])
w("();\n")
w("// connect ports\n")
for c in components:
for pm in c.port_map:
w(c.name.val)
w('.')
assert isinstance(pm, HdlOp) and\
pm.fn == HdlOpType.MAP_ASSOCIATION, pm
mod_port, connected_sig = pm.ops
assert isinstance(mod_port, HdlValueId), mod_port
self.visit_iHdlExpr(mod_port)
assert isinstance(connected_sig,
HdlValueId), connected_sig
w("(")
self.visit_iHdlExpr(connected_sig)
w(");\n")
w("}\n")
w("};\n")
