def as_hdl_HdlPortItem(self, o: HdlPortItem):
i = o.getInternSig()._interface
d = o.direction
if isinstance(i, Clk):
assert i._dtype.bit_length() == 1, i
if d == DIRECTION.IN:
t = self.sc_in_clk
elif d == DIRECTION.OUT:
t = self.sc_out_clk
elif d == DIRECTION.INOUT:
t = self.sc_inout_clk
else:
raise ValueError(d)
else:
if d == DIRECTION.IN:
pt = self.sc_in
elif d == DIRECTION.OUT:
pt = self.sc_out
elif d == DIRECTION.INOUT:
pt = self.sc_inout
else:
raise ValueError(d)
t = self.as_hdl_HdlType(o._dtype)
t = HdlOp(HdlOpType.PARAMETRIZATION, [pt, t])
var = HdlIdDef()
var.direction = HWT_TO_HDLCONVEROTR_DIRECTION[o.direction]
s = o.getInternSig()
var.name = s.name
var.origin = o
var.type = t
return var
def as_hdl_PortConnection(self, o: HdlPortItem):
assert isinstance(o, HdlPortItem), o
intern, outer = o.getInternSig(), o.getOuterSig()
assert not intern.hidden, intern
assert not outer.hidden, outer
intern_hdl = HdlValueId(intern.name, obj=intern)
outer_hdl = HdlValueId(outer.name, obj=outer)
pm = hdl_map_asoc(intern_hdl, outer_hdl)
return pm
def as_hdl_PortConnection(self, o: HdlPortItem):
assert isinstance(o, HdlPortItem), o
if o.dst._dtype != o.src._dtype:
raise SerializerException(
f"Port map {o.name:s} is not valid (types does not match) ({o.src._dtype}, {o.dst._dtype}) "
f"{o.src} => {o.dst}")
intern, outer = o.getInternSig(), o.getOuterSig()
intern_hdl = self.as_hdl_Value(intern)
intern_hdl.obj = o
outer_hdl = self.as_hdl_Value(outer)
pm = hdl_map_asoc(intern_hdl, outer_hdl)
return pm
def as_hdl_PortConnection(self, o: HdlPortItem):
assert isinstance(o, HdlPortItem), o
if o.dst._dtype != o.src._dtype:
raise SerializerException(
"Port map %s is not valid (types does not match) (%r, %r) "
"%s => %s" % (o.name, o.src._dtype,
o.dst._dtype, o.src, o.dst,)
)
intern, outer = o.getInternSig(), o.getOuterSig()
intern_hdl = self.as_hdl_Value(intern)
intern_hdl.obj = o
outer_hdl = self.as_hdl_Value(outer)
pm = hdl_map_asoc(intern_hdl, outer_hdl)
return pm
def as_hdl_HdlPortItem(self, o: HdlPortItem):
var = HdlIdDef()
var.direction = HWT_TO_HDLCONVEROTR_DIRECTION[o.direction]
s = o.getInternSig()
var.name = s.name
var.origin = o
var.type = o._dtype
return self.as_hdl_HdlModuleDef_variable(var, (), None, None, None, None)
def portItemfromSignal(s: SignalItem, component, d: DIRECTION):
pi = HdlPortItem(s.name, d, s._dtype, component)
# if not hasattr(s, '_interface'):
# # dummy signal for the case we are converting a netlist which is not wrapped in :class:`hwt.synthesizer.unit.Unit` instance
# from hwt.interfaces.std import Signal
# t = s._dtype
# s._interface = Signal(dtype=t)
# pi._interface = s._interface
return pi
def portItemfromSignal(s: SignalItem, component, d: DIRECTION):
return HdlPortItem(s.name, d, s._dtype, component)