def setUp(self):
SimTestCase.setUp(self)
u = self.u = HsJoinFairShare(Handshaked)
self.INPUTS = 3
u.INPUTS.set(self.INPUTS)
u.DATA_WIDTH.set(8)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
SimTestCase.setUp(self)
u = self.u = HsJoinFairShare(Handshaked)
self.INPUTS = 3
u.INPUTS.set(self.INPUTS)
u.DATA_WIDTH.set(8)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
super(RStrictOrderInterconnectTC, self).setUp()
u = self.u = RStrictOrderInterconnect()
self.DRIVERS_CNT = 3
u.DRIVER_CNT.set(self.DRIVERS_CNT)
self.MAX_TRANS_OVERLAP = 4
u.MAX_TRANS_OVERLAP.set(self.MAX_TRANS_OVERLAP)
self.DATA_WIDTH = 64
u.DATA_WIDTH.set(self.DATA_WIDTH)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
super(RStrictOrderInterconnectTC, self).setUp()
u = self.u = RStrictOrderInterconnect()
self.DRIVERS_CNT = 3
u.DRIVER_CNT.set(self.DRIVERS_CNT)
self.MAX_TRANS_OVERLAP = 4
u.MAX_TRANS_OVERLAP.set(self.MAX_TRANS_OVERLAP)
self.DATA_WIDTH = 64
u.DATA_WIDTH.set(self.DATA_WIDTH)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
self.u = CLinkedListWriter()
self.ITEMS_IN_BLOCK = 31
self.PTR_WIDTH = 8
self.BUFFER_CAPACITY = 7
self.TIMEOUT = 40
self.ID = int(self.u.ID)
self.MAX_LEN = self.BUFFER_CAPACITY // 2 - 1
self.DATA_WIDTH = int(self.u.DATA_WIDTH)
self.u.TIMEOUT.set(self.TIMEOUT)
self.u.ITEMS_IN_BLOCK.set(self.ITEMS_IN_BLOCK)
self.u.PTR_WIDTH.set(self.PTR_WIDTH)
self.u.BUFFER_CAPACITY.set(self.BUFFER_CAPACITY)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
self.u = CLinkedListWriter()
self.ITEMS_IN_BLOCK = 31
self.PTR_WIDTH = 8
self.BUFFER_CAPACITY = 7
self.TIMEOUT = 40
self.ID = int(self.u.ID)
self.MAX_LEN = self.BUFFER_CAPACITY // 2 - 1
self.DATA_WIDTH = int(self.u.DATA_WIDTH)
self.u.TIMEOUT.set(self.TIMEOUT)
self.u.ITEMS_IN_BLOCK.set(self.ITEMS_IN_BLOCK)
self.u.PTR_WIDTH.set(self.PTR_WIDTH)
self.u.BUFFER_CAPACITY.set(self.BUFFER_CAPACITY)
_, self.model, self.procs = simPrepare(self.u)
def setUp(self):
super(CLinkedListReaderTC, self).setUp()
u = self.u = CLinkedListReader()
self.ITEMS_IN_BLOCK = 31
self.PTR_WIDTH = 8
self.BUFFER_CAPACITY = 8
self.DATA_WIDTH = 64
self.ID = int(self.u.ID)
self.ID_LAST = int(self.u.ID_LAST)
self.MAX_LEN = self.BUFFER_CAPACITY // 2 - 1
u.ITEMS_IN_BLOCK.set(self.ITEMS_IN_BLOCK)
u.PTR_WIDTH.set(self.PTR_WIDTH)
u.BUFFER_CAPACITY.set(self.BUFFER_CAPACITY)
u.DATA_WIDTH.set(self.DATA_WIDTH)
_, self.model, self.procs = simPrepare(self.u)
def prepareUnit(self,
unit,
modelCls=None,
dumpModelIn=None,
onAfterToRtl=None):
"""
Create simulation model and connect it with interfaces of original unit
and decorate it with agents and collect all simulation processes
:param unit: interface level unit which you wont prepare for simulation
:param modelCls: class of rtl simulation model to run simulation on, if is None
rtl sim model will be generated from unit
:param dumpModelIn: folder to where put sim model files (if is None sim model will be constructed only in memory)
:param onAfterToRtl: callback fn(unit) which will be called unit after it will
be synthesised to rtl
"""
self.u, self.model, self.procs = simPrepare(unit,
modelCls=modelCls,
dumpModelIn=dumpModelIn,
onAfterToRtl=onAfterToRtl)
def setUp(self):
u = OneHotToBinSimWrap()
self.ONE_HOT_WIDTH = 8
u.ONE_HOT_WIDTH.set(self.ONE_HOT_WIDTH)
self.u, self.model, self.procs = simPrepare(u)
def setUp(self):
u = OneHotToBinSimWrap()
self.ONE_HOT_WIDTH = 8
u.ONE_HOT_WIDTH.set(self.ONE_HOT_WIDTH)
self.u, self.model, self.procs = simPrepare(u)
def setUpUnit(self, u):
self.u, self.model, self.procs = simPrepare(u)