def Slice_valAsHdl(cls, t, val: SliceVal, ctx: HwtSerializerCtx): if val._isFullVld(): return "%d:%d" % (evalParam(val.val[0]).val, evalParam( val.val[1]).val) else: return "SliceVal((%d, %d), SLICE, %d)" % (evalParam( val.val[0]).val, evalParam(val.val[1]).val, val.vldMask)
def paramsToValTuple(unit): d = {} for p in unit._params: name = p.getName(unit) v = evalParam(p) d[name] = v return freeze_dict(d)
def serializeVar(v): dv = evalParam(v.defaultVal) if isinstance(dv, EnumVal): dv = "%s.%s" % (dv._dtype.name, dv.val) else: dv = cls.Value(dv) return v.name, cls.HdlType(v._dtype), dv
def getVectorFromType(self, dtype) -> Union[bool, None, Tuple[int, int]]: """ :see: doc of method on parent class """ if dtype == BIT: return False elif isinstance(dtype, Bits): return [evalParam(dtype.width) - 1, hInt(0)]
def serializeVar(v): dv = evalParam(v.defVal) if isinstance(dv, HEnumVal): dv = "%s.%s" % (dv._dtype.name, dv.val) else: dv = cls.Value(dv, ctx) return v.name, cls.HdlType(v._dtype, childCtx), dv
def SignalItem(cls, si, declaration=False): if declaration: raise NotImplementedError() else: if isinstance(si, Param): return cls.Value(evalParam(si)) if si.hidden and hasattr(si, "origin"): return cls.asHdl(si.origin) else: return "self.%s._oldVal" % si.name
def _loadFromArray(self, dtype: HdlType, bitAddr: int) -> int: """ Parse HArray type to this transaction template instance :return: address of it's end """ self.itemCnt = evalParam(dtype.size).val self.children = TransTmpl(dtype.elmType, 0, parent=self, origin=self.origin) return bitAddr + self.itemCnt * self.children.bitAddrEnd
def log2ceil(x): """ Returns no of bits required to store x-1 for example x=8 returns 3 """ if not isinstance(x, (int, float)): x = evalParam(x).val if x == 0 or x == 1: res = 1 else: res = math.ceil(math.log2(x)) return hInt(res)
def _copyParamsAndInterfaces(self): for p in self._baseUnit._params: myP = Param(evalParam(p)) self._registerParameter(p.name, myP) object.__setattr__(self, myP.name, myP) origToWrapInfMap = {} for intf in self.baseUnit._interfaces: if intf._multipliedBy is not None: for i in range(evalParam(intf._multipliedBy).val): myIntf = cloneIntf(intf) name = intf._name + "_%d" % i self._registerInterface(name, myIntf) object.__setattr__(self, name, myIntf) try: ia = origToWrapInfMap[intf] except KeyError: ia = [] origToWrapInfMap[intf] = ia ia.append(myIntf) else: myIntf = cloneIntf(intf) self._registerInterface(intf._name, myIntf) object.__setattr__(self, intf._name, myIntf) origToWrapInfMap[intf] = myIntf for i in self._interfaces: self._loadInterface(i, True) return origToWrapInfMap
def SignalItem(cls, si: SignalItem, ctx: HwtSerializerCtx, declaration=False): if declaration: raise NotImplementedError() else: if isinstance(si, Param): return cls.Value(evalParam(si), ctx) # elif isinstance(si, SignalItem) and si._const: # return cls.Value(si._val, ctx) elif si.hidden and hasattr(si, "origin"): return cls.asHdl(si.origin, ctx) else: return "%s" % si.name
def HdlType_bits(cls, typ, declaration=False): if typ.signed is None: if not (typ.forceVector or typ.bit_length() > 1): return 'SIM_BIT' c = typ.constrain if isinstance(c, (int, float)): pass else: c = evalParam(c) if isinstance(c, SliceVal): c = c._size() else: c = c.val return "simBitsT(%d, %r)" % (c, typ.signed)
def HdlType_bits(cls, typ, ctx, declaration=False): assert not declaration if typ.signed is None: if not (typ.forceVector or typ.bit_length() > 1): return 'SIM_BIT' w = typ.width if isinstance(w, int): pass else: w = evalParam(w) assert isinstance(w, IntegerVal) assert w._isFullVld() w = w.val return "simBitsT(%d, %r)" % (w, typ.signed)
def autoAddAgents(unit): """ Walk all interfaces on unit and instantiate actor for every interface. :return: all monitor/driver functions which should be added to simulation as processes """ proc = [] for intf in unit._interfaces: if not intf._isExtern: continue try: agentCls = intf._getSimAgent() except NotImplementedError: raise NotImplementedError( ("Interface %s\n" + "has not any simulation agent class assigned") % (str(intf))) if intf._multipliedBy is not None: agentCnt = evalParam(intf._multipliedBy).val agent = [] for i in range(agentCnt): a = agentCls(intf[i]) agent.append(a) intf[i]._ag = a else: agent = agentCls(intf) intf._ag = agent if intf._multipliedBy is None: agent = [ agent, ] if intf._direction == INTF_DIRECTION.MASTER: agProcs = list(map(lambda a: a.getMonitors(), agent)) elif intf._direction == INTF_DIRECTION.SLAVE: agProcs = list(map(lambda a: a.getDrivers(), agent)) else: raise NotImplementedError("intf._direction %s for %r" % (str(intf._direction), intf)) for p in agProcs: proc.extend(p) return proc
def fromPy(cls, val, typeObj): size = evalParam(typeObj.size) if isinstance(size, Value): size = size.val if val is None: v = typeObj.elmType.fromPy(None) elements = [v.clone() for _ in range(size)] else: elements = [] for v in val: if isinstance(v, RtlSignalBase): # is signal assert v._dtype == typeObj.elmType e = v else: e = typeObj.elmType.fromPy(v) elements.append(e) return cls(elements, typeObj, int(val is not None))
def HdlType_bits(cls, typ, ctx, declaration=False): if declaration: raise NotImplementedError() w = typ.width if isinstance(w, int): pass else: w = evalParam(w) assert isinstance(w, IntegerVal) assert w._isFullVld() w = w.val iItems = ["%d" % w] if typ.signed is not BITS_DEFAUTL_SIGNED: iItems.append("signed=%r" % typ.signed) if typ.forceVector is not BITS_DEFAUTL_FORCEVECTOR: iItems.append("forceVector=%r" % typ.forceVector) if typ.negated is not BITS_DEFAUTL_NEGATED: iItems.append("negated=%r" % typ.negated) return "Bits(%s)" % (", ".join(iItems))
def fromPy(cls, val, typeObj, vldMask=None): """ :param val: None or dictionary {index:value} or iterrable of values :param vldMask: if is None validity is resolved from val if is 0 value is invalidated if is 1 value has to be valid """ size = evalParam(typeObj.size) if isinstance(size, Value): size = int(size) elements = {} if vldMask == 0: val = None if val is None: pass elif isinstance(val, dict): for k, v in val.items(): if not isinstance(k, int): k = int(k) elements[k] = typeObj.elmType.fromPy(v) else: for k, v in enumerate(val): if isinstance(v, RtlSignalBase): # is signal assert v._dtype == typeObj.elmType e = v else: e = typeObj.elmType.fromPy(v) elements[k] = e _mask = int(bool(val)) if vldMask is None: vldMask = _mask else: assert (vldMask == _mask) return cls(elements, typeObj, vldMask)
def _entPort2CompPort(e, p): port = Port() port.name = p.name port.direction = p.direction.name.lower() port.type = WireTypeDef() t = port.type dt = p._dtype t.typeName = VhdlSerializer.HdlType(dt, VhdlSerializer.getBaseContext()) try: t.typeName = t.typeName[:t.typeName.index('(')] except ValueError: pass if dt == BIT: port.vector = False elif isinstance(dt, Bits): port.vector = [evalParam(dt.width) - 1, hInt(0)] t.viewNameRefs = [ "xilinx_vhdlsynthesis", "xilinx_vhdlbehavioralsimulation" ] return port
def _copyParamsAndInterfaces(self): for p in self._baseUnit._params: myP = Param(evalParam(p)) self._registerParameter(p.name, myP) object.__setattr__(self, myP.name, myP) origToWrapInfMap = {} for intf in self.baseUnit._interfaces: # clone interface myIntf = intf._clone() # subinterfaces are not instanciated yet # myIntf._direction = intf._direction myIntf._direction = INTF_DIRECTION.opposite(intf._direction) self._registerInterface(intf._name, myIntf) object.__setattr__(self, intf._name, myIntf) origToWrapInfMap[intf] = myIntf for i in self._interfaces: self._loadInterface(i, True) return origToWrapInfMap
def _copyParamsAndInterfaces(self): for p in self._baseUnit._params: myP = Param(evalParam(p)) self._registerParameter(p.name, myP) object.__setattr__(self, myP.name, myP) origToWrapInfMap = {} for intf in self.baseUnit._interfaces: # clone interface myIntf = intf._clone() # subinterfaces are not instanciated yet # myIntf._direction = intf._direction myIntf._direction = INTF_DIRECTION.opposite(intf._direction) self._registerInterface(intf._name, myIntf) object.__setattr__(self, intf._name, myIntf) origToWrapInfMap[intf] = myIntf for i in self._interfaces: self._loadInterface(i, True) return origToWrapInfMap
def vec(val, width, signed=None): """create hdl vector value""" assert val < evalParam(hInt(2)._pow(width)).val return vecT(width, signed).fromPy(val)
def HdlType_array(cls, typ, scope, declaration=False): assert not declaration return "Array(%s, %d)" % (cls.HdlType(typ.elmType), evalParam( typ.size).val)
def getVal(): v = evalParam(g.defVal) if v.vldMask: return v.val else: return 0
def Slice_valAsHdl(cls, t, val, ctx): return "SliceVal((simHInt(%d), simHInt(%d)), SLICE, %d)" % (evalParam( val.val[0]).val, evalParam(val.val[1]).val, val.vldMask)
def _getAddrStep(self): """ :return: how many bits is one unit of address (f.e. 8 bits for char * pointer, 36 for 36 bit bram) """ return evalParam(self.DATA_WIDTH).val