def test_RtlSignal(self):
ctx = RtlNetlist()
a = ctx.sig("a", uint8_t)
b = ctx.sig("b", uint8_t)
ae = self.ae
ae(a, "a")
ae(b, "b")
ae(~a, "~a")
c = ctx.sig("c", int8_t)
ae(-c, "-c")
ae(a + b, "a + b")
ae(a - b, "a - b")
ae(a // b, "a // b")
ae(a * b, "a * b")
ae(a._eq(b), "a._eq(b)")
ae(a != b, "a != b")
ae(a > b, "a > b")
ae(a >= b, "a >= b")
ae(a <= b, "a <= b")
ae(a < b, "a < b")
d = ctx.sig("d", Bits(8))
ae(d[1:0], "d[1:0]")
ae(d << 1, "Concat(d[7:0], Bits(1).from_py(0))")
ae(d >> 1, "Concat(Bits(1).from_py(0), d[8:1])")
def AxiReaderCore():
n = RtlNetlist()
rSt_t = HEnum('rSt_t', ['rdIdle', 'rdData'])
rSt = n.sig('rSt', rSt_t)
arRd = n.sig('arRd')
arVld = n.sig('arVld')
rVld = n.sig('rVld')
rRd = n.sig('rRd')
# ar fsm next
If(arRd,
# rdIdle
If(arVld,
rSt(rSt_t.rdData)
).Else(
rSt(rSt_t.rdIdle)
)
).Else(
# rdData
If(rRd & rVld,
rSt(rSt_t.rdIdle)
).Else(
rSt(rSt_t.rdData)
)
)
return n, [rSt, arRd, arVld, rVld, rRd]
def SwitchStatement():
t = Bits(8)
n = RtlNetlist()
In = n.sig("input", t, def_val=8)
Out = n.sig("output", t)
Switch(In).add_cases([(i, Out(i + 1)) for i in range(8)])
interf = {In: DIRECTION.IN, Out: DIRECTION.OUT}
return n, interf
def SwitchStatement():
t = Bits(8)
n = RtlNetlist()
In = n.sig("input", t, defVal=8)
Out = n.sig("output", t)
Switch(In).addCases([(i, Out(i + 1)) for i in range(8)])
interf = [In, Out]
return n, interf
def SwitchStatement():
t = Bits(8)
n = RtlNetlist()
In = n.sig("input", t, defVal=8)
Out = n.sig("output", t)
Switch(In).addCases(
[(i, Out(i + 1)) for i in range(8)]
)
interf = [In, Out]
return n, interf
def IndexOps():
t = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
s_out = n.sig("s_out", t)
s_in2 = n.sig("s_in2", t)
s_out2 = n.sig("s_out2", t)
s_in3 = n.sig("s_in3", Bits(16))
s_out3 = n.sig("s_out3", t)
s_in4a = n.sig("s_in4a", t)
s_in4b = n.sig("s_in4b", t)
s_out4 = n.sig("s_out4", Bits(16))
s_out(s_in[4:]._concat(vec(2, 4)))
s_out2[4:](s_in2[4:])
s_out2[:4](s_in2[:4])
s_out3(s_in3[8:])
s_out4[8:](s_in4a)
s_out4[(8 + 8):8](s_in4b)
interf = [s_in, s_out, s_in2, s_out2, s_in3, s_out3, s_in4a, s_in4b, s_out4]
return n, interf
def IndexOps():
t = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
s_out = n.sig("s_out", t)
s_in2 = n.sig("s_in2", t)
s_out2 = n.sig("s_out2", t)
s_in3 = n.sig("s_in3", Bits(16))
s_out3 = n.sig("s_out3", t)
s_in4a = n.sig("s_in4a", t)
s_in4b = n.sig("s_in4b", t)
s_out4 = n.sig("s_out4", Bits(16))
s_out(s_in[4:]._concat(vec(2, 4)))
s_out2[4:](s_in2[4:])
s_out2[:4](s_in2[:4])
s_out3(s_in3[8:])
s_out4[8:](s_in4a)
s_out4[(8 + 8):8](s_in4b)
interf = [
s_in, s_out, s_in2, s_out2, s_in3, s_out3, s_in4a, s_in4b, s_out4
]
return n, interf
def test_SwitchContainer_try_reduce__empty(self):
nl = RtlNetlist()
a = nl.sig("a", BIT)
s0 = Switch(a).add_cases([(hBit(0), []), (hBit(1), [])])
s0_red, io_change = s0._try_reduce()
self.assertFalse(io_change)
self.assertEqual(s0_red, [])
def Counter():
t = Bits(8)
n = RtlNetlist("LeadingZero")
en = n.sig("en")
rst = n.sig("rst")
clk = n.sig("clk")
s_out = n.sig("s_out", t)
cnt = n.sig("cnt", t, clk=clk, syncRst=rst, defVal=0)
If(en, cnt(cnt + 1))
s_out(cnt)
interf = [rst, clk, s_out, en]
return n, interf
def SimpleWhile():
t = Bits(8)
n = RtlNetlist()
boundary = n.sig("boundary", t, def_val=8)
s_out = n.sig("s_out", t)
start = n.sig("start")
en = n.sig("en")
clk = n.sig("clk")
syncRst = n.sig("rst")
counter = n.sig("counter", t, clk, syncRst, 0)
If(start, counter(boundary)).Elif(en, counter(counter - 1))
s_out(counter)
interf = {
clk: DIRECTION.IN,
syncRst: DIRECTION.IN,
start: DIRECTION.IN,
en: DIRECTION.IN,
s_out: DIRECTION.OUT
}
return n, interf
def Counter():
t = Bits(8)
n = RtlNetlist("LeadingZero")
en = n.sig("en")
rst = n.sig("rst")
clk = n.sig("clk")
s_out = n.sig("s_out", t)
cnt = n.sig("cnt", t, clk=clk, syncRst=rst, defVal=0)
If(en,
cnt(cnt + 1)
)
s_out(cnt)
interf = [rst, clk, s_out, en]
return n, interf
def test_slice_bits_sig(self):
n = RtlNetlist()
sig = n.sig("sig", uint8_t, defVal=128)
with self.assertRaises(IndexError):
self.assertEqual(sig[8], hBit(1))
self.assertEqual(sig[7], hBit(1))
self.assertStrEq(sig[7], "sig(7)")
self.assertEqual(sig[1], hBit(0))
self.assertStrEq(sig[1], "sig(1)")
self.assertEqual(sig[0], hBit(0))
self.assertStrEq(sig[0], "sig(0)")
with self.assertRaises(IndexError):
self.assertEqual(sig[-1], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:-1], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:0], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[0:], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[0:0], hBit(0))
self.assertEqual(sig[8:], sig)
self.assertStrEq(sig[8:], "sig")
self.assertEqual(sig[8:0], sig)
self.assertStrEq(sig[8:0], "sig")
self.assertEqual(sig[:0], sig)
self.assertStrEq(sig[:0], "sig")
self.assertEqual(sig[:1], vec(64, 7))
self.assertStrEq(sig[:1], "sig(7DOWNTO1)")
self.assertEqual(sig[:2], vec(32, 6))
self.assertStrEq(sig[:2], "sig(7DOWNTO2)")
self.assertEqual(sig[:7], vec(1, 1))
self.assertStrEq(sig[:7], "sig(7DOWNTO7)")
self.assertEqual(sig[7:6], vec(0, 1))
self.assertStrEq(sig[7:6], "sig(6DOWNTO6)")
def test_slice_bits_sig(self):
n = RtlNetlist()
sig = n.sig("sig", uint8_t, defVal=128)
with self.assertRaises(IndexError):
self.assertEqual(sig[8], hBit(1))
self.assertEqual(sig[7], hBit(1))
self.assertStrEq(sig[7], "sig(7)")
self.assertEqual(sig[1], hBit(0))
self.assertStrEq(sig[1], "sig(1)")
self.assertEqual(sig[0], hBit(0))
self.assertStrEq(sig[0], "sig(0)")
with self.assertRaises(IndexError):
self.assertEqual(sig[-1], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:-1], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[9:0], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[0:], hBit(0))
with self.assertRaises(IndexError):
self.assertEqual(sig[0:0], hBit(0))
self.assertEqual(sig[8:], sig)
self.assertStrEq(sig[8:], "sig")
self.assertEqual(sig[8:0], sig)
self.assertStrEq(sig[8:0], "sig")
self.assertEqual(sig[:0], sig)
self.assertStrEq(sig[:0], "sig")
self.assertEqual(sig[:1], vec(64, 7))
self.assertStrEq(sig[:1], "sig(7DOWNTO1)")
self.assertEqual(sig[:2], vec(32, 6))
self.assertStrEq(sig[:2], "sig(7DOWNTO2)")
self.assertEqual(sig[:7], vec(1, 1))
self.assertStrEq(sig[:7], "sig(7DOWNTO7)")
self.assertEqual(sig[7:6], vec(0, 1))
self.assertStrEq(sig[7:6], "sig(6DOWNTO6)")
def LeadingZero():
t = Bits(64)
resT = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
index = n.sig("s_indexOfFirstZero", resT)
leadingZeroTop = None # index is index of first empty record or last one
for i in reversed(range(8)):
connections = index(i)
if leadingZeroTop is None:
leadingZeroTop = connections
else:
leadingZeroTop = If(s_in[i]._eq(0),
connections).Else(leadingZeroTop)
interf = [s_in, index]
return n, interf
def SimpleRegister():
t = Bits(8)
n = RtlNetlist()
s_out = n.sig("s_out", t)
s_in = n.sig("s_in", t)
clk = n.sig("clk")
syncRst = n.sig("rst")
val = n.sig("val", t, clk, syncRst, 0)
val(s_in)
s_out(val)
interf = {
clk: DIRECTION.IN,
syncRst: DIRECTION.IN,
s_in: DIRECTION.IN,
s_out: DIRECTION.OUT
}
return n, interf
def AxiReaderCore():
n = RtlNetlist()
rSt_t = HEnum('rSt_t', ['rdIdle', 'rdData'])
rSt = n.sig('rSt', rSt_t)
r_idle = n.sig("r_idle")
arRd = n.sig('arRd')
arVld = n.sig('arVld')
rVld = n.sig('rVld')
rRd = n.sig('rRd')
# ar fsm next
If(arRd,
# rdIdle
If(arVld,
rSt(rSt_t.rdData)
).Else(
rSt(rSt_t.rdIdle)
)
).Else(
# rdData
If(rRd & rVld,
rSt(rSt_t.rdIdle)
).Else(
rSt(rSt_t.rdData)
)
)
r_idle(rSt._eq(rSt_t.rdIdle))
return n, {
r_idle: DIRECTION.OUT,
arRd: DIRECTION.IN,
arVld: DIRECTION.IN,
rVld: DIRECTION.IN,
rRd: DIRECTION.IN
}
def test_SwitchContainer_try_reduce__all(self):
nl = RtlNetlist()
a = nl.sig("a", BIT)
b = nl.sig("b", BIT)
s0 = Switch(a).add_cases([(hBit(0), [
b(0),
]), (hBit(1), [
b(0),
])])
s0_red, io_change = s0._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(s0_red), 1)
self.assertTrue(s0_red[0].isSame(b(0)))
def test_ifContSeqEval(self):
for a_in, b_in in [(0, 0), (0, 1), (1, 0), (1, 1)]:
resT = Bits(2)
nl = RtlNetlist()
res = nl.sig("res", resT)
a = nl.sig("a", BIT)
b = nl.sig("b", BIT)
def w(val):
return res(val)
a.def_val = hBit(a_in)
b.def_val = hBit(b_in)
stm = IfContainer(a & b,
ifTrue=[
res(0),
],
elIfs=[
(a, [res(1)]),
],
ifFalse=[
res(2),
])
if a_in and b_in:
expected = 0
elif a_in:
expected = 1
else:
expected = 2
stm.seqEval()
newVal = res._val
self.assertEqual(newVal.val, expected)
self.assertEqual(newVal.vld_mask, 3)
def Counter():
t = Bits(8)
n = RtlNetlist("LeadingZero")
en = n.sig("en")
rst = n.sig("rst")
clk = n.sig("clk")
s_out = n.sig("s_out", t)
cnt = n.sig("cnt", t, clk=clk, syncRst=rst, def_val=0)
If(en, cnt(cnt + 1))
s_out(cnt)
interf = {
rst: DIRECTION.IN,
clk: DIRECTION.IN,
s_out: DIRECTION.OUT,
en: DIRECTION.IN
}
return n, interf
def LeadingZero():
t = Bits(64)
resT = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
index = n.sig("s_indexOfFirstZero", resT)
leadingZeroTop = None # index is index of first empty record or last one
for i in reversed(range(8)):
connections = index(i)
if leadingZeroTop is None:
leadingZeroTop = connections
else:
leadingZeroTop = If(s_in[i]._eq(0),
connections
).Else(
leadingZeroTop
)
interf = [s_in, index]
return n, interf
def SimpleEnum():
t = Bits(8)
fsmT = HEnum('fsmT', ['send0', 'send1'])
n = RtlNetlist()
s_out = n.sig("s_out", t)
s_in0 = n.sig("s_in0", t)
s_in1 = n.sig("s_in1", t)
clk = n.sig("clk")
syncRst = n.sig("rst")
fsmSt = n.sig("fsmSt", fsmT, clk, syncRst, fsmT.send0)
If(fsmSt._eq(fsmT.send0),
s_out(s_in0),
fsmSt(fsmT.send1),
).Else(
s_out(s_in1),
fsmSt(fsmT.send0)
)
interf = [clk, syncRst, s_in0, s_in1, s_out]
return n, interf
def test_ifContSeqEval(self):
for a_in, b_in in [(0, 0),
(0, 1),
(1, 0),
(1, 1)]:
resT = Bits(2)
nl = RtlNetlist()
res = nl.sig("res", resT)
a = nl.sig("a", BIT)
b = nl.sig("b", BIT)
def w(val):
return res(val)
a.defVal = hBit(a_in)
b.defVal = hBit(b_in)
stm = IfContainer(a & b,
ifTrue=[res(0), ],
elIfs=[(a, [res(1)]), ],
ifFalse=[res(2), ]
)
if a_in and b_in:
expected = 0
elif a_in:
expected = 1
else:
expected = 2
stm.seqEval()
newVal = res._val
self.assertEqual(newVal.val, expected)
self.assertEqual(newVal.vldMask, 3)
class StatementTreesInternalTC(unittest.TestCase):
def setUp(self):
unittest.TestCase.setUp(self)
self.n = RtlNetlist("test")
def test_getBaseCond(self):
a = self.n.sig('a')
_a = getBaseCond(~a)
self.assertIs(a, _a[0])
self.assertIs(True, _a[1])
_a = getBaseCond(a)
self.assertIs(a, _a[0])
self.assertIs(False, _a[1])
b = a < self.n.sig('b')
_b = getBaseCond(~b)
self.assertIs(b, _b[0])
self.assertIs(True, _b[1])
_b = getBaseCond(b)
self.assertIs(b, _b[0])
self.assertIs(False, _b[1])
def test_If(self):
ctx = RtlNetlist()
a = ctx.sig("a", uint8_t)
b = ctx.sig("b", uint8_t)
stm = If(a != 0,
a(b)
).Else(
a(b + 1)
)
self.ae(stm, """\
If(a != 0,
a(b)
).Else(
a(b + 1)
)""")
stm = If(a != 2,
a(b)
).Elif(b != 3,
a(b - 1)
).Else(
a(b + 2)
)
self.ae(stm, """\
If(a != 2,
a(b)
).Elif(b != 3,
a(b - 1)
).Else(
a(b + 2)
)""")
stm = If(a != 2,
a(b)
).Elif(b != 3,
a(b - 1)
).Elif(b != 4,
a(b - 2)
)
self.ae(stm, """\
If(a != 2,
a(b)
).Elif(b != 3,
a(b - 1)
).Elif(b != 4,
a(b - 2)
)""")
def IndexOps():
t = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
s_out = n.sig("s_out", t)
s_in2 = n.sig("s_in2", t)
s_out2 = n.sig("s_out2", t)
s_in3 = n.sig("s_in3", Bits(16))
s_out3 = n.sig("s_out3", t)
s_in4a = n.sig("s_in4a", t)
s_in4b = n.sig("s_in4b", t)
s_out4 = n.sig("s_out4", Bits(16))
s_out(s_in[4:]._concat(Bits(4).from_py(2)))
s_out2[4:](s_in2[4:])
s_out2[:4](s_in2[:4])
s_out3(s_in3[8:])
s_out4[8:](s_in4a)
s_out4[(8 + 8):8](s_in4b)
interf = {
s_in: DIRECTION.IN,
s_out: DIRECTION.OUT,
s_in2: DIRECTION.IN,
s_out2: DIRECTION.OUT,
s_in3: DIRECTION.IN,
s_out3: DIRECTION.OUT,
s_in4a: DIRECTION.IN,
s_in4b: DIRECTION.IN,
s_out4: DIRECTION.OUT
}
return n, interf
def test_Switch(self):
ctx = RtlNetlist()
a = ctx.sig("a", uint8_t)
b = ctx.sig("b", uint8_t)
stm = Switch(a)\
.Case(0, b(0))\
.Case(1, b(1))\
.Case(2, b(2))\
.Default(b(3))
self.ae(stm, """\
Switch(a)\\
.Case(0,
b(0))\\
.Case(1,
b(1))\\
.Case(2,
b(2))\\
.Default(
b(3))""")
def ComplexConditions():
n = RtlNetlist()
stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait", "ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, def_val=stT.idle)
s_idle = n.sig('s_idle')
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1, st(stT.lenExtr)).Elif(sd0, st(stT.ts1Wait)).Elif(
sd1, st(stT.ts0Wait)).Else(ifNoTsRd)
Switch(st)\
.Case(stT.idle,
tsWaitLogic(
If(cntrlFifoVld,
st(stT.tsWait)
)
)
).Case(stT.tsWait,
tsWaitLogic(st(st))
).Case(stT.ts0Wait,
If(sd0,
st(stT.lenExtr)
)
).Case(stT.ts1Wait,
If(sd1,
st(stT.lenExtr)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
st(stT.idle)
)
)
s_idle(st._eq(stT.idle))
return n, {
rst: DIRECTION.IN,
clk: DIRECTION.IN,
sd0: DIRECTION.IN,
sd1: DIRECTION.IN,
cntrlFifoVld: DIRECTION.IN,
cntrlFifoLast: DIRECTION.IN,
s_idle: DIRECTION.OUT
}
def ComplexConditions():
n = RtlNetlist()
stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait", "ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle)
s_idle = n.sig('s_idle')
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1,
st(stT.lenExtr)
).Elif(sd0,
st(stT.ts1Wait)
).Elif(sd1,
st(stT.ts0Wait)
).Else(
ifNoTsRd
)
Switch(st)\
.Case(stT.idle,
tsWaitLogic(
If(cntrlFifoVld,
st(stT.tsWait)
)
)
).Case(stT.tsWait,
tsWaitLogic(st(st))
).Case(stT.ts0Wait,
If(sd0,
st(stT.lenExtr)
)
).Case(stT.ts1Wait,
If(sd1,
st(stT.lenExtr)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
st(stT.idle)
)
)
s_idle(st._eq(stT.idle))
return n, [rst, clk, sd0, sd1, cntrlFifoVld, cntrlFifoLast, s_idle]
def SimpleWhile():
t = Bits(8)
n = RtlNetlist()
boundary = n.sig("boundary", t, defVal=8)
s_out = n.sig("s_out", t)
start = n.sig("start")
en = n.sig("en")
clk = n.sig("clk")
syncRst = n.sig("rst")
counter = n.sig("counter", t, clk, syncRst, 0)
If(start, counter(boundary)).Elif(en, counter(counter - 1))
s_out(counter)
interf = [clk, syncRst, start, en, s_out]
return n, interf
def SimpleWhile():
t = Bits(8)
n = RtlNetlist()
boundary = n.sig("boundary", t, defVal=8)
s_out = n.sig("s_out", t)
start = n.sig("start")
en = n.sig("en")
clk = n.sig("clk")
syncRst = n.sig("rst")
counter = n.sig("counter", t, clk, syncRst, 0)
If(start,
counter(boundary)
).Elif(en,
counter(counter - 1)
)
s_out(counter)
interf = [clk, syncRst, start, en, s_out]
return n, interf
def test_SwitchContainer_cut_off_drivers_of(self):
nl = RtlNetlist()
a = nl.sig("a", BIT)
b = nl.sig("b", BIT)
c = nl.sig("c", BIT)
# reduce everything
s0 = Switch(a).add_cases([(hBit(0), [
b(0),
])])
s0_0 = s0._cut_off_drivers_of(b)
self.assertIs(s0, s0_0)
s0_1 = Switch(a).add_cases([(hBit(0), [
b(0),
])])
self.assertTrue(s0.isSame(s0_1))
# reduce nothing
s0 = Switch(a).add_cases([(hBit(0), [
b(0),
])])
s0_0 = s0._cut_off_drivers_of(a)
self.assertIsNone(s0_0)
self.assertTrue(s0.isSame(s0_1))
# reduce a single case
s1 = Switch(a).add_cases([
(hBit(0), [
b(0),
]),
(hBit(1), [
c(0),
]),
])
s1_0 = s1._cut_off_drivers_of(c)
s1_cut = Switch(a).add_cases([
(hBit(1), [
c(0),
]),
])
self.assertTrue(s1_0.isSame(s1_cut))
self.assertSetEqual(set(s1._outputs), {b})
self.assertSetEqual(set(s1_0._outputs), {c})
self.assertTrue(s1.isSame(s0))
# reduce default
s2 = Switch(a).add_cases([
(hBit(0), [
b(1),
]),
(hBit(1), [
b(0),
]),
]).Default(c(1))
s2_0 = s2._cut_off_drivers_of(c)
s2_rem = Switch(a).add_cases([
(hBit(0), [
b(1),
]),
(hBit(1), [
b(0),
]),
])
s2_cut = Switch(a).add_cases([
(hBit(0), []),
(hBit(1), []),
]).Default(c(1))
self.assertTrue(s2.isSame(s2_rem))
self.assertTrue(s2_0.isSame(s2_cut))
def test_bits_sig_slice_on_slice_of_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][7:0][2:0], s[2:0])
self.assertIs(s[10:0][7:0][4:1], s[4:1])
self.assertIs(s[12:5][7:1][4:1], s[10:7])
class OperatorTC(unittest.TestCase):
def setUp(self):
unittest.TestCase.setUp(self)
self.n = RtlNetlist()
def test_BoolNot(self):
for v in [True, False]:
res = ~hBool(v)
self.assertEqual(res.val, not v)
self.assertEqual(res.vldMask, 1)
self.assertEqual(res.updateTime, -1)
def test_BitNot(self):
for v in [False, True]:
res = ~hBit(v)
self.assertEqual(res.val, int(not v))
self.assertEqual(res.vldMask, 1)
self.assertEqual(res.updateTime, -1)
def _test_And(self, vals):
for a, b, expected in andTable:
res = vals[a] & vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
self.assertEqual(
expectedRes.val, res.val,
"%r & %r val=%r (should be %r)" %
(a, b, res.val, expectedRes.val))
self.assertEqual(
expectedRes.vldMask, res.vldMask,
"%r & %r vldMask=%r (should be %r)" %
(a, b, res.vldMask, expectedRes.vldMask))
def _test_Or(self, vals):
for a, b, expected in orTable:
res = vals[a] | vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
self.assertEqual(
expectedRes.val, res.val,
"%r | %r val=%r (should be %r)" %
(a, b, res.val, expectedRes.val))
self.assertEqual(
expectedRes.vldMask, res.vldMask,
"%r | %r vldMask=%r (should be %r)" %
(a, b, res.vldMask, expectedRes.vldMask))
def _test_Xor(self, vals):
for a, b, expected in xorTable:
res = vals[a] ^ vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
if expectedRes.vldMask:
self.assertEqual(
expectedRes.val, res.val,
"%r ^ %r val=%r (should be %r)" %
(a, b, res.val, expectedRes.val))
self.assertEqual(
expectedRes.vldMask, res.vldMask,
"%r ^ %r vldMask=%r (should be %r)" %
(a, b, res.vldMask, expectedRes.vldMask))
def test_BoolAnd(self):
self._test_And(boolvals)
def test_BitAnd(self):
self._test_And(bitvals)
def test_BoolOr(self):
self._test_Or(boolvals)
def test_BitOr(self):
self._test_Or(bitvals)
def test_BoolXor(self):
self._test_Xor(boolvals)
def test_BitXor(self):
self._test_Xor(bitvals)
def test_notNotIsOrigSig(self):
a = self.n.sig("a")
self.assertIs(a, ~~a)
def test_downto(self):
a = self.n.sig('a', dtype=INT)
a.defVal = hInt(10)
b = hInt(0)
r = a._downto(b)
res = r.staticEval()
self.assertEqual(res.val[0].val, 10)
self.assertEqual(res.val[1].val, 0)
def test_ADD_InvalidOperands(self):
a = self.n.sig('a', dtype=STR)
b = self.n.sig('b')
self.assertRaises(Exception, lambda: a + b)
def test_ADD_IntBits(self):
a = vec(7, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
a = vec(7, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
def test_AND_eval(self):
for a_in, b_in, out in [(0, 0, 0), (0, 1, 0), (1, 0, 0), (1, 1, 1)]:
res = hBit(a_in) & hBit(b_in)
self.assertEqual(res.vldMask, 1)
self.assertEqual(res.val, out,
"a_in %d, b_in %d, out %d" % (a_in, b_in, out))
def test_ADD_eval(self):
for a_in, b_in, out in [(0, 0, 0), (0, 1, 1), (1, 0, 1), (1, 1, 2)]:
res = hInt(a_in) + hInt(b_in)
b_w = 2
self.assertTrue(res.vldMask)
self.assertEqual(res.val, out,
"a_in %d, b_in %d, out %d" % (a_in, b_in, out))
resBit = vec(a_in, b_w) + vec(b_in, b_w)
self.assertEqual(resBit.vldMask, 3)
self.assertEqual(resBit.val, out,
"a_in %d, b_in %d, out %d" % (a_in, b_in, out))
def test_bits_le(self):
a = vec(8, 8)
b = vec(16, 8)
self.assertTrue((a <= b).val)
self.assertFalse((b <= a).val)
def test_bits_sig_slice_on_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][2:0], s[2:0])
self.assertIs(s[10:0][4:1], s[4:1])
self.assertIs(s[12:5][4:1], s[9:6])
def test_bits_sig_slice_on_slice_of_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][7:0][2:0], s[2:0])
self.assertIs(s[10:0][7:0][4:1], s[4:1])
self.assertIs(s[12:5][7:1][4:1], s[10:7])
def test_bits_mul(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
s * 10
s * s
def test_array_eq_neq(self):
t = Bits(8)[5]
v0 = t.fromPy(range(5))
v1 = t.fromPy({0: 10, 1: 2})
v2 = t.fromPy([1, 2, 3, 4, 5])
self.assertTrue(v0._eq(v0))
with self.assertRaises(ValueError):
self.assertNotEqual(v0, v1)
self.assertNotEqual(v0, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v1)
self.assertTrue(v2, v2)
def test_int_neg(self):
self.assertEqual(int(INT.fromPy(-10)), -10)
self.assertEqual(int(-INT.fromPy(10)), -10)
self.assertEqual(int(-INT.fromPy(10)), -10)
v = -INT.fromPy(None)
self.assertEqual(v.val, 0)
self.assertEqual(v.vldMask, 0)
def test_int_to_bool(self):
self.assertFalse(bool(INT.fromPy(0)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(1)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(-11)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(500)._auto_cast(BOOL)))
with self.assertRaises(ValueError):
bool(INT.fromPy(None)._auto_cast(BOOL))
def test_bits_mul(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
s * 10
s * s
def test_bits_sig_slice_on_slice_of_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][7:0][2:0], s[2:0])
self.assertIs(s[10:0][7:0][4:1], s[4:1])
self.assertIs(s[12:5][7:1][4:1], s[10:7])
#!/usr/bin/env python3alu
# -*- coding: utf-8 -*-
import unittest
from hwt.bitmask import mask
from hwt.hdl.typeShortcuts import hInt, hBool, hBit, vec
from hwt.hdl.types.bits import Bits
from hwt.hdl.types.bool import HBool
from hwt.hdl.types.defs import INT, STR, BOOL
from hwt.synthesizer.rtlLevel.mainBases import RtlSignalBase
from hwt.synthesizer.rtlLevel.netlist import RtlNetlist
n = RtlNetlist()
s0 = n.sig("s0", HBool())
s1 = n.sig("s1")
andTable = [(None, None, None),
(None, 0, 0),
(None, 1, None),
(0, None, 0),
(0, 0, 0),
(0, 1, 0),
(1, 1, 1),
(s0, 1, s0),
(s0, 0, 0),
(1, s0, s0),
(0, s0, 0),
]
orTable = [(None, None, None),
def test_SwitchContainer_isSame(self):
nl = RtlNetlist()
a = nl.sig("a", BIT)
b = nl.sig("b", BIT)
s0 = SwitchContainer(switchOn=a, cases=[(hBit(0), [
b(0),
])])
s1 = SwitchContainer(switchOn=a, cases=[(hBit(0), [
b(0),
])])
self.assertTrue(s0.isSame(s1))
self.assertTrue(s1.isSame(s0))
s2 = SwitchContainer(switchOn=a,
cases=[
(hBit(0), [
b(0),
]),
(hBit(1), [
b(0),
]),
])
self.assertFalse(s0.isSame(s2))
self.assertFalse(s2.isSame(s0))
s2b = SwitchContainer(switchOn=a,
cases=[
(hBit(0), [
b(0),
]),
(hBit(1), [
b(0),
]),
])
self.assertTrue(s2.isSame(s2b))
self.assertTrue(s2b.isSame(s2))
s3 = SwitchContainer(switchOn=a, cases=[
(hBit(1), [
b(0),
]),
])
self.assertFalse(s0.isSame(s3))
self.assertFalse(s3.isSame(s0))
s4 = SwitchContainer(switchOn=a,
cases=[(hBit(0), [
b(0),
])],
default=[
b(0),
])
self.assertFalse(s0.isSame(s4))
self.assertFalse(s4.isSame(s0))
s5 = SwitchContainer(switchOn=a,
cases=[(hBit(0), [
b(0),
])],
default=[
b(1),
])
self.assertFalse(s4.isSame(s5))
self.assertFalse(s5.isSame(s4))
def test_bits_mul(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
s * 10
s * s
class OperatorTC(unittest.TestCase):
def setUp(self):
unittest.TestCase.setUp(self)
self.n = RtlNetlist()
def test_BoolNot(self):
for v in [True, False]:
res = ~hBool(v)
self.assertEqual(res.val, not v)
self.assertEqual(res.vldMask, 1)
self.assertEqual(res.updateTime, -1)
def test_BitNot(self):
for v in [False, True]:
res = ~hBit(v)
self.assertEqual(res.val, int(not v))
self.assertEqual(res.vldMask, 1)
self.assertEqual(res.updateTime, -1)
def _test_And(self, vals):
for a, b, expected in andTable:
res = vals[a] & vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
self.assertEqual(expectedRes.val, res.val,
"%r & %r val=%r (should be %r)"
% (a, b, res.val, expectedRes.val))
self.assertEqual(expectedRes.vldMask, res.vldMask,
"%r & %r vldMask=%r (should be %r)"
% (a, b, res.vldMask, expectedRes.vldMask))
def _test_Or(self, vals):
for a, b, expected in orTable:
res = vals[a] | vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
self.assertEqual(expectedRes.val, res.val,
"%r | %r val=%r (should be %r)"
% (a, b, res.val, expectedRes.val))
self.assertEqual(expectedRes.vldMask, res.vldMask,
"%r | %r vldMask=%r (should be %r)"
% (a, b, res.vldMask, expectedRes.vldMask))
def _test_Xor(self, vals):
for a, b, expected in xorTable:
res = vals[a] ^ vals[b]
expectedRes = vals[expected]
if isinstance(expectedRes, RtlSignalBase):
self.assertIs(res, expectedRes)
else:
if expectedRes.vldMask:
self.assertEqual(expectedRes.val, res.val,
"%r ^ %r val=%r (should be %r)"
% (a, b, res.val, expectedRes.val))
self.assertEqual(expectedRes.vldMask, res.vldMask,
"%r ^ %r vldMask=%r (should be %r)"
% (a, b, res.vldMask, expectedRes.vldMask))
def test_BoolAnd(self):
self._test_And(boolvals)
def test_BitAnd(self):
self._test_And(bitvals)
def test_BoolOr(self):
self._test_Or(boolvals)
def test_BitOr(self):
self._test_Or(bitvals)
def test_BoolXor(self):
self._test_Xor(boolvals)
def test_BitXor(self):
self._test_Xor(bitvals)
def test_notNotIsOrigSig(self):
a = self.n.sig("a")
self.assertIs(a, ~ ~a)
def test_downto(self):
a = self.n.sig('a', dtype=INT)
a.defVal = hInt(10)
b = hInt(0)
r = a._downto(b)
res = r.staticEval()
self.assertEqual(res.val[0].val, 10)
self.assertEqual(res.val[1].val, 0)
def test_ADD_InvalidOperands(self):
a = self.n.sig('a', dtype=STR)
b = self.n.sig('b')
self.assertRaises(Exception, lambda: a + b)
def test_ADD_IntBits(self):
a = vec(7, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
a = vec(7, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
def test_AND_eval(self):
for a_in, b_in, out in [(0, 0, 0),
(0, 1, 0),
(1, 0, 0),
(1, 1, 1)]:
res = hBit(a_in) & hBit(b_in)
self.assertEqual(res.vldMask, 1)
self.assertEqual(
res.val, out,
"a_in %d, b_in %d, out %d"
% (a_in, b_in, out))
def test_ADD_eval(self):
for a_in, b_in, out in [(0, 0, 0),
(0, 1, 1),
(1, 0, 1),
(1, 1, 2)]:
res = hInt(a_in) + hInt(b_in)
b_w = 2
self.assertTrue(res.vldMask)
self.assertEqual(
res.val, out,
"a_in %d, b_in %d, out %d"
% (a_in, b_in, out))
resBit = vec(a_in, b_w) + vec(b_in, b_w)
self.assertEqual(resBit.vldMask, 3)
self.assertEqual(
resBit.val, out,
"a_in %d, b_in %d, out %d"
% (a_in, b_in, out))
def test_bits_le(self):
a = vec(8, 8)
b = vec(16, 8)
self.assertTrue((a <= b).val)
self.assertFalse((b <= a).val)
def test_bits_sig_slice_on_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][2:0], s[2:0])
self.assertIs(s[10:0][4:1], s[4:1])
self.assertIs(s[12:5][4:1], s[9:6])
def test_bits_sig_slice_on_slice_of_slice(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
self.assertIs(s[10:0][7:0][2:0], s[2:0])
self.assertIs(s[10:0][7:0][4:1], s[4:1])
self.assertIs(s[12:5][7:1][4:1], s[10:7])
def test_bits_mul(self):
n = RtlNetlist()
s = n.sig("s", Bits(16))
s * 10
s * s
def test_array_eq_neq(self):
t = Bits(8)[5]
v0 = t.fromPy(range(5))
v1 = t.fromPy({0: 10, 1: 2})
v2 = t.fromPy([1, 2, 3, 4, 5])
self.assertTrue(v0._eq(v0))
with self.assertRaises(ValueError):
self.assertNotEqual(v0, v1)
self.assertNotEqual(v0, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v1)
self.assertTrue(v2, v2)
def test_int_neg(self):
self.assertEqual(int(INT.fromPy(-10)), -10)
self.assertEqual(int(-INT.fromPy(10)), -10)
self.assertEqual(int(-INT.fromPy(10)), -10)
v = -INT.fromPy(None)
self.assertEqual(v.val, 0)
self.assertEqual(v.vldMask, 0)
def test_int_to_bool(self):
self.assertFalse(bool(INT.fromPy(0)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(1)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(-11)._auto_cast(BOOL)))
self.assertTrue(bool(INT.fromPy(500)._auto_cast(BOOL)))
with self.assertRaises(ValueError):
bool(INT.fromPy(None)._auto_cast(BOOL))
def setUp(self):
unittest.TestCase.setUp(self)
nl = RtlNetlist()
self.a = nl.sig("a")
self.b = nl.sig("b")
self.c = nl.sig("c")
class BasicSynthesisTC(unittest.TestCase):
def setUp(self):
unittest.TestCase.setUp(self)
self.n = RtlNetlist()
def test_opRisingEdgeMultipletimesSameObj(self):
clk = self.n.sig("ap_clk")
self.assertEqual(clk._onRisingEdge(), clk._onRisingEdge())
def test_syncSig(self):
n = self.n
clk = n.sig("ap_clk")
a = n.sig("a", clk=clk)
self.assertEqual(len(a.drivers), 1)
_if = a.drivers[0]
self.assertIsInstance(_if, If)
self.assertEqual(len(_if.ifTrue), 1)
self.assertEqual(_if.ifFalse, None)
self.assertEqual(len(_if.elIfs), 0)
assig = _if.ifTrue[0]
self.assertEqual(assig.src, a.next)
self.assertEqual(assig.dst, a)
self.assertIs(_if.cond, clk._onRisingEdge())
def test_syncSigWithReset(self):
c = self.n
clk = c.sig("ap_clk")
rst = c.sig("ap_rst")
a = c.sig("a", clk=clk, syncRst=rst, defVal=0)
self.assertEqual(len(a.drivers), 1)
_if = a.drivers[0]
self.assertIsInstance(_if, If)
self.assertIs(_if.cond, clk._onRisingEdge())
self.assertEqual(len(_if.ifTrue), 1)
self.assertEqual(_if.ifFalse, None)
self.assertEqual(len(_if.elIfs), 0)
if_reset = _if.ifTrue[0]
self.assertIs(if_reset.cond, rst._isOn())
self.assertEqual(len(if_reset.ifTrue), 1)
self.assertEqual(len(if_reset.ifFalse), 1)
self.assertEqual(len(if_reset.elIfs), 0)
a_reset = if_reset.ifTrue[0]
a_next = if_reset.ifFalse[0]
self.assertIsInstance(a_reset, Assignment)
self.assertEqual(a_reset.src, hBit(0))
self.assertIsInstance(a_next, Assignment)
self.assertEqual(a_next.src, a.next)
def test_indexOps(self):
c, interf = IndexOps()
_, arch = list(c.synthesize("indexOps", interf, DummyPlatform()))
s = VhdlSerializer.Architecture(arch, VhdlSerializer.getBaseContext())
self.assertNotIn("sig_", s)
#!/usr/bin/env python3alu
# -*- coding: utf-8 -*-
import unittest
from hwt.bitmask import mask
from hwt.hdl.typeShortcuts import hInt, hBool, hBit, vec
from hwt.hdl.types.bits import Bits
from hwt.hdl.types.bool import HBool
from hwt.hdl.types.defs import INT, STR, BOOL
from hwt.synthesizer.rtlLevel.mainBases import RtlSignalBase
from hwt.synthesizer.rtlLevel.netlist import RtlNetlist
n = RtlNetlist()
s0 = n.sig("s0", HBool())
s1 = n.sig("s1")
andTable = [
(None, None, None),
(None, 0, 0),
(None, 1, None),
(0, None, 0),
(0, 0, 0),
(0, 1, 0),
(1, 1, 1),
(s0, 1, s0),
(s0, 0, 0),
(1, s0, s0),
(0, s0, 0),
]
orTable = [
def _signalsForInterface(self,
ctx: RtlNetlist,
res: Optional[Dict[RtlSignal, DIRECTION]],
name_scope: Optional[NameScope],
prefix='',
typeTransform=None,
reverse_dir=False):
"""
Generate RtlSignal _sig and HdlPortInstance _hdl_port
for each interface which has no subinterface
:note: if already has _sig return use it instead
:param ctx: instance of RtlNetlist where signals should be created
:param res: output dictionary where result should be stored
:param prefix: name prefix for created signals
:param name_scope: name scope used to check colisions on port names
if this a current top (every component is checked
when it is seen first time)
:param typeTransform: optional function (type) returns modified type
for signal
"""
if self._interfaces:
for intf in self._interfaces:
intf._signalsForInterface(ctx,
res,
name_scope,
prefix=prefix,
typeTransform=typeTransform,
reverse_dir=reverse_dir)
else:
assert self._sig is None, self
t = self._dtype
if typeTransform is not None:
t = typeTransform(t)
s = ctx.sig(prefix + self._getPhysicalName(), t)
s._interface = self
self._sig = s
if self._isExtern:
d = INTF_DIRECTION.asDirection(self._direction)
u = ctx.parent
if reverse_dir:
d = DIRECTION.opposite(d)
assert self._hdl_port is None, (
"Now creating a hdl interface for top"
" it but seems that it was already created")
if res is not None:
res[s] = d
if reverse_dir:
pi = portItemfromSignal(s, u, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
ctx.ent.ports.append(pi)
else:
pi = self._hdl_port
# port of some subcomponent which names were already checked
pi.connectOuterSig(s)
self._hdl_port = pi
class StatementTreesTC(unittest.TestCase):
def setUp(self):
unittest.TestCase.setUp(self)
self.n = RtlNetlist()
def compareStructure(self, template, cont):
self.assertIsInstance(cont, template.__class__)
if isinstance(template, IfContainer):
self.assertEqual(template.cond, cont.cond)
self.assertEqual(len(template.ifTrue), len(template.ifTrue))
self.assertEqual(len(template.elIfs), len(template.elIfs))
self.assertEqual(len(template.ifFalse), len(template.ifFalse))
elif isinstance(template, SwitchContainer):
self.assertEqual(template.switchOn, template.switchOn)
self.assertEqual(len(template.cases), len(template.cases))
def strStructureCmp(self, cont, tmpl):
if not isinstance(cont, str):
cont = VhdlSerializer.asHdl(cont, VhdlSerializer.getBaseContext())
_tmpl = rmWhitespaces.sub(" ", tmpl).strip()
_cont = rmWhitespaces.sub(" ", cont).strip()
self.assertEqual(_tmpl, _cont)
def test_baicIf(self):
a = self.n.sig('a')
b = self.n.sig('b')
obj = If(a,
b(1)
).Else(
b(0)
)
container, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(container), 1)
container = container[0]
tmpl = IfContainer(a,
ifTrue=[b(1)],
ifFalse=[b(0)])
self.compareStructure(tmpl, container)
def test_basicSwitch(self):
a = self.n.sig('a', dtype=INT)
b = self.n.sig('b', dtype=INT)
obj = Switch(a).addCases([(i, c(i, b)) for i in range(4)])
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = SwitchContainer(a, [(i, c(i, b)) for i in range(3)]
+ [(None, c(3, b))])
self.compareStructure(tmpl, cont)
def test_ifsInSwitch(self):
n = self.n
stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait",
"ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle)
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic():
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Else(
c(stT.ts1Wait, st)
)
obj = Switch(st)\
.Case(stT.idle,
tsWaitLogic()
).Case(stT.tsWait,
tsWaitLogic()
).Case(stT.ts0Wait,
If(sd0,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.ts1Wait,
If(sd1,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
c(stT.idle, st)
).Else(
c(st, st)
)
)
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = """
CASE st IS
WHEN idle =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= ts1Wait;
END IF;
WHEN tsWait =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= ts1Wait;
END IF;
WHEN ts0Wait =>
IF sd0 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts1Wait =>
IF sd1 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE
"""
self.strStructureCmp(cont, tmpl)
def test_ifs2LvlInSwitch(self):
n = self.n
stT = HEnum('t_state', ["idle", "tsWait",
"ts0Wait", "ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle)
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Else(
ifNoTsRd
)
obj = Switch(st)\
.Case(stT.idle,
tsWaitLogic(
If(cntrlFifoVld,
c(stT.tsWait, st)
).Else(
c(st, st)
)
)
).Case(stT.tsWait,
tsWaitLogic(c(st, st))
).Case(stT.ts0Wait,
If(sd0,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.ts1Wait,
If(sd1,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
c(stT.idle, st)
).Else(
c(st, st)
)
)
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = """
CASE st IS
WHEN idle =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSIF ctrlFifoVld = '1' THEN
st_next <= tsWait;
ELSE
st_next <= st;
END IF;
WHEN tsWait =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts0Wait =>
IF sd0 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts1Wait =>
IF sd1 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE
"""
self.strStructureCmp(cont, tmpl)
def test_ifs3LvlInSwitch(self):
n = self.n
stT = HEnum('t_state', ["idle", "tsWait",
"ts0Wait", "ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle)
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Elif(sd0,
c(stT.ts1Wait, st)
).Else(
ifNoTsRd
)
obj = Switch(st)\
.Case(stT.idle,
tsWaitLogic(
If(cntrlFifoVld,
c(stT.tsWait, st)
).Else(
c(st, st)
)
)
).Case(stT.tsWait,
tsWaitLogic(c(st, st))
).Case(stT.ts0Wait,
If(sd0,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.ts1Wait,
If(sd1,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
c(stT.idle, st)
).Else(
c(st, st)
)
)
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = """
CASE st IS
WHEN idle =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSIF sd0 = '1' THEN
st_next <= ts1Wait;
ELSIF ctrlFifoVld = '1' THEN
st_next <= tsWait;
ELSE
st_next <= st;
END IF;
WHEN tsWait =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSIF sd0 = '1' THEN
st_next <= ts1Wait;
ELSE
st_next <= st;
END IF;
WHEN ts0Wait =>
IF sd0 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts1Wait =>
IF sd1 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE
"""
self.strStructureCmp(cont, tmpl)