Ejemplo n.º 1
0
    def sig(self,
            name,
            dtype=BIT,
            clk=None,
            syncRst=None,
            def_val=None,
            nop_val=NO_NOPVAL) -> Union[RtlSignal, RtlSyncSignal]:
        """
        Create new signal in this context

        :param clk: clk signal, if specified signal is synthesized
            as SyncSignal
        :param syncRst: synchronous reset signal
        :param def_val: default value used for reset and intialization
        :param nop_val: value used a a driver if signal is not driven by any driver
        """
        _def_val = self._try_cast_any_to_HdlType(def_val, dtype)
        if nop_val is not NO_NOPVAL:
            nop_val = self._try_cast_any_to_HdlType(nop_val, dtype)

        if clk is not None:
            s = RtlSyncSignal(self, name, dtype, _def_val, nop_val)
            if syncRst is not None and def_val is None:
                raise SigLvlConfErr(
                    "Probably forgotten default value on sync signal %s", name)
            if syncRst is not None:
                r = If(syncRst._isOn(), RtlSignal.__call__(s, _def_val)).Else(
                    RtlSignal.__call__(s, s.next))
            else:
                r = [RtlSignal.__call__(s, s.next)]

            if isinstance(clk, (InterfaceBase, RtlSignal)):
                clk_trigger = clk._onRisingEdge()
            else:
                # has to be tuple of (clk_sig, AllOps.RISING/FALLING_EDGE)
                clk, clk_edge = clk
                if clk_edge is AllOps.RISING_EDGE:
                    clk_trigger = clk._onRisingEdge()
                elif clk_edge is AllOps.FALLING_EDGE:
                    clk_trigger = clk._onRisingEdge()
                else:
                    raise ValueError("Invalid clock edge specification",
                                     clk_edge)

            If(clk_trigger, r)
        else:
            if syncRst:
                raise SigLvlConfErr("Signal %s has reset but has no clk" %
                                    name)
            s = RtlSignal(self, name, dtype, def_val=_def_val, nop_val=nop_val)

        return s
Ejemplo n.º 2
0
    def sig(self, name, dtype=BIT, clk=None, syncRst=None, def_val=None):
        """
        Create new signal in this context

        :param clk: clk signal, if specified signal is synthesized
            as SyncSignal
        :param syncRst: synchronous reset signal
        """
        if isinstance(def_val, RtlSignal):
            assert def_val._const, \
                "Initial value of register has to be constant"
            _def_val = def_val._auto_cast(dtype)
        elif isinstance(def_val, Value):
            _def_val = def_val._auto_cast(dtype)
        elif isinstance(def_val, InterfaceBase):
            _def_val = def_val._sig
        else:
            _def_val = dtype.from_py(def_val)

        if clk is not None:
            s = RtlSyncSignal(self, name, dtype, _def_val)
            if syncRst is not None and def_val is None:
                raise SigLvlConfErr(
                    "Probably forgotten default value on sync signal %s", name)
            if syncRst is not None:
                r = If(syncRst._isOn(),
                       RtlSignal.__call__(s, _def_val)
                       ).Else(
                    RtlSignal.__call__(s, s.next)
                )
            else:
                r = [RtlSignal.__call__(s, s.next)]

            If(clk._onRisingEdge(),
               r
               )
        else:
            if syncRst:
                raise SigLvlConfErr(
                    "Signal %s has reset but has no clk" % name)
            s = RtlSignal(self, name, dtype, def_val=_def_val)

        self.signals.add(s)

        return s