def __init__(self, cmpFn=lambda x, y: x < y):
"""
:param cmpFn: function (item0, item1) if returns true,
items are not swaped
"""
Unit.__init__(self)
self.cmpFn = cmpFn
def __init__(self, cmpFn=lambda x, y: x < y):
"""
:param cmpFn: function (item0, item1) if returns true,
items are not swaped
"""
Unit.__init__(self)
self.cmpFn = cmpFn
def __init__(self, intfCls: Type[VldSynced]):
"""
:param hsIntfCls: class of interface which should be used
as interface of this unit
"""
self.intfCls = intfCls
Unit.__init__(self)
def synthesised(u: Unit, targetPlatform=DummyPlatform()):
assert not u._wasSynthetised()
if not hasattr(u, "_interfaces"):
u._loadDeclarations()
for _ in u._toRtl(targetPlatform):
pass
return u
def synthesised(u: Unit, targetPlatform=DummyPlatform()):
assert not u._wasSynthetised()
if not hasattr(u, "_interfaces"):
u._loadDeclarations()
for _ in u._toRtl(targetPlatform):
pass
return u
def do_serialize(self, unit: Unit) -> bool:
orig = unit._serializeDecision
if orig is _serializeExclude_eval:
unit._serializeDecision = None
try:
return super(SerializerFilterDoNotExclude, self).do_serialize(unit)
finally:
unit._serializeDecision = orig
def __init__(self, hsIntfCls: Type[Union[Handshaked, HandshakeSync]]):
"""
:param hsIntfCls: class of interface which should be used
as interface of this unit
"""
assert(issubclass(hsIntfCls, (Handshaked, HandshakeSync))), hsIntfCls
self.intfCls = hsIntfCls
Unit.__init__(self)
def __init__(self, parent: Unit,
outInterface: Union[Handshaked, VldSynced],
en: RtlSignal,
exclusiveEn: Optional[RtlSignal]=None):
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self.pendingReg = parent._reg(outInterface._name + "_pending_", defVal=1)
ack = self.outInterface.rd
self._ack = parent._sig(outInterface._name + "_ack")
self._ack(ack | ~self.pendingReg)
def synthesised(u: Unit, target_platform=DummyPlatform()):
"""
Elaborate design without producing any HDL
"""
sm = StoreManager(DummySerializerConfig,
_filter=SerializerFilterDoNotExclude())
if not hasattr(u, "_interfaces"):
u._loadDeclarations()
for _ in u._to_rtl(target_platform, sm):
pass
return u
def __init__(self,
parent: Unit,
outInterface: Union[Handshaked, VldSynced],
en: RtlSignal,
exclusiveEn: Optional[RtlSignal] = None):
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self.pendingReg = parent._reg(outInterface._name + "_pending_",
defVal=1)
ack = self.outInterface.rd
self._ack = parent._sig(outInterface._name + "_ack")
self._ack(ack | ~self.pendingReg)
def __init__(self, structT, tmpl=None, frames=None):
"""
:param structT: instance of HStruct which specifies data format to download
:param tmpl: instance of TransTmpl for this structT
:param frames: list of FrameTmpl instances for this tmpl
:note: if tmpl and frames are None they are resolved from structT parseTemplate
:note: this unit can parse sequence of frames, if they are specified by "frames"
:attention: interfaces for each field in struct will be dynamically created
:attention: structT can not contain fields with variable size like HStream
"""
Unit.__init__(self)
assert isinstance(structT, HStruct)
TemplateConfigured.__init__(self, structT, tmpl=tmpl, frames=frames)
def build(cls,
unit: Unit,
unique_name: str,
build_dir: Optional[str],
target_platform=DummyPlatform(),
do_compile=True) -> "BasicRtlSimulatorVcd":
"""
Create a pycocotb.basic_hdl_simulator based simulation model
for specified unit and load it to python
:param unit: interface level unit which you wont prepare for simulation
:param unique_name: unique name for build directory and python module with simulator
:param target_platform: target platform for this synthesis
:param build_dir: directory to store sim model build files,
if None sim model will be constructed only in memory
"""
if unique_name is None:
unique_name = unit._getDefaultName()
_filter = SerializerFilterDoNotExclude()
if build_dir is None or not do_compile:
buff = StringIO()
store_man = SaveToStream(SimModelSerializer, buff, _filter=_filter)
else:
if not os.path.isabs(build_dir):
build_dir = os.path.join(os.getcwd(), build_dir)
build_private_dir = os.path.join(build_dir, unique_name)
store_man = SaveToFilesFlat(SimModelSerializer,
build_private_dir,
_filter=_filter)
store_man.module_path_prefix = unique_name
to_rtl(unit,
name=unique_name,
target_platform=target_platform,
store_manager=store_man)
if build_dir is not None:
d = build_dir
dInPath = d in sys.path
if not dInPath:
sys.path.insert(0, d)
if unique_name in sys.modules:
del sys.modules[unique_name]
simModule = importlib.import_module(
unique_name + "." + unique_name,
package='simModule_' + unique_name)
if not dInPath:
sys.path.pop(0)
else:
simModule = ModuleType('simModule_' + unique_name)
# python supports only ~100 opened brackets
# if exceeded it throws MemoryError: s_push: parser stack overflow
exec(buff.getvalue(), simModule.__dict__)
model_cls = simModule.__dict__[unit._name]
# can not use just function as it would get bounded to class
return cls(model_cls, unit)
def __init__(self, structTemplate, intfCls=None, shouldEnterFn=None):
"""
:param structTemplate: instance of HStruct which describes
address space of this endpoint
:param intfCls: class of bus interface which should be used
:param shouldEnterFn: function(structField) return (shouldEnter, shouldUse)
where shouldEnter is flag that means iterator over this interface
should look inside of this actual object
and shouldUse flag means that this field should be used
(to create interface)
"""
assert intfCls is not None, "intfCls has to be specified"
self._intfCls = intfCls
self.STRUCT_TEMPLATE = structTemplate
if shouldEnterFn is None:
self.shouldEnterFn = self._defaultShouldEnterFn
else:
self.shouldEnterFn = shouldEnterFn
Unit.__init__(self)
def _instantiateTimerTickLogic(parentUnit: Unit, timer: RtlSignal,
origMaxVal: Union[int, RtlSignal, Value],
enableSig: Optional[RtlSignal],
rstSig: Optional[RtlSignal]) -> RtlSignal:
"""
Instantiate logic of this timer
:return: tick signal from this timer
"""
r = timer.cntrRegister
tick = r._eq(0)
if enableSig is None:
if rstSig is None:
If(tick,
r(origMaxVal)
).Else(
r(r - 1)
)
else:
If(rstSig | tick,
r(origMaxVal)
).Else(
r(r - 1)
)
else:
if rstSig is None:
If(enableSig,
If(tick,
r(origMaxVal)
).Else(
r(r - 1)
)
)
else:
If(rstSig | (enableSig & tick),
r(origMaxVal)
).Elif(enableSig,
r(r - 1)
)
if enableSig is not None:
tick = (tick & enableSig)
if rstSig is not None:
tick = (tick & ~rstSig)
if timer.name:
# wrap tick in signal
s = parentUnit._sig(timer.name)
s(tick)
tick = s
return tick
def __init__(self, parent: Unit, outInterface: Union[Handshaked,
VldSynced],
en: RtlSignal, exclusiveEn: Optional[RtlSignal]):
self.parent = parent
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self._ready = self.outInterface.rd
self._ack = parent._sig(outInterface._name + "_ack")
self._valid = self.outInterface.vld
def __init__(self, structT, tmpl=None, frames=None):
"""
:param structT: instance of HStruct which specifies data format to download
:param tmpl: instance of TransTmpl for this structT
:param frames: list of FrameTmpl instances for this tmpl
:note: if tmpl and frames are None they are resolved from structT parseTemplate
:note: this unit can parse sequence of frames, if they are specified by "frames"
:attention: interfaces for each field in struct will be dynamically created
:attention: structT can not contain fields with variable size like HStream
"""
Unit.__init__(self)
assert isinstance(structT, HStruct)
self._structT = structT
if tmpl is not None:
assert frames is not None, "tmpl and frames can be used only together"
else:
assert frames is None, "tmpl and frames can be used only together"
self._tmpl = tmpl
self._frames = frames
def __init__(self, structTemplate, intfCls=None, shouldEnterFn=None):
"""
:param structTemplate: instance of HStruct which describes
address space of this endpoint
:param intfCls: class of bus interface which should be used
:param shouldEnterFn: function(root_t, structFieldPath) return (shouldEnter, shouldUse)
where shouldEnter is flag that means iterator over this interface
should look inside of this actual object
and shouldUse flag means that this field should be used
(to create interface)
"""
assert intfCls is not None, "intfCls has to be specified"
self._intfCls = intfCls
self.STRUCT_TEMPLATE = structTemplate
if shouldEnterFn is None:
self.shouldEnterFn = self._defaultShouldEnterFn
else:
self.shouldEnterFn = shouldEnterFn
Unit.__init__(self)
def __init__(self, parent: Unit, outInterface: AxiStream, en: RtlSignal,
exclusiveEn: Optional[RtlSignal],
streamGroup: OutStreamNodeGroup):
self.streamGroup = streamGroup
self.parent = parent
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self._ready = self.outInterface.ready
self._ack = parent._sig(outInterface._name + "_ack")
self._valid = self.outInterface.valid
streamGroup.members.append(self)
def __init__(self, topUnit: Unit, name: str=None,
extraVhdlFiles: List[str]=[],
extraVerilogFiles: List[str]=[],
serializer=VhdlSerializer,
targetPlatform=DummyPlatform()):
"""
:param topObj: Unit instance of top component
:param name: optional name of top
:param extraVhdlFiles: list of extra vhdl file names for files
which should be distributed in this IP-core
:param extraVerilogFiles: same as extraVhdlFiles just for Verilog
:param serializer: serializer which specifies target HDL language
:param targetPlatform: specifies properties of target platform, like available resources, vendor, etc.
"""
assert not topUnit._wasSynthetised()
if not name:
name = topUnit._getDefaultName()
super(IpPackager, self).__init__(
topUnit, name, extraVhdlFiles, extraVerilogFiles)
self.serializer = serializer
self.targetPlatform = targetPlatform
def toBasicSimulatorSimModel(unit: Unit,
unique_name: str,
build_dir: Optional[str],
target_platform=DummyPlatform(),
do_compile=True):
"""
Create a pycocotb.basic_hdl_simulator based simulation model
for specified unit and load it to python
:param unit: interface level unit which you wont prepare for simulation
:param unique_name: unique name for build directory and python module with simulator
:param target_platform: target platform for this synthesis
:param build_dir: directory to store sim model build files,
if None sim model will be constructed only in memory
"""
if unique_name is None:
unique_name = unit._getDefaultName()
if build_dir is not None:
build_private_dir = os.path.join(os.getcwd(), build_dir, unique_name)
else:
build_private_dir = None
sim_code = toRtl(unit,
name=unique_name,
targetPlatform=target_platform,
saveTo=build_private_dir,
serializer=SimModelSerializer)
if build_dir is not None:
d = os.path.join(os.getcwd(), build_dir)
dInPath = d in sys.path
if not dInPath:
sys.path.insert(0, d)
if unique_name in sys.modules:
del sys.modules[unique_name]
simModule = importlib.import_module(unique_name + "." + unique_name,
package='simModule_' + unique_name)
if not dInPath:
sys.path.pop(0)
else:
simModule = ModuleType('simModule_' + unique_name)
# python supports only ~100 opened brackets
# if exceded it throws MemoryError: s_push: parser stack overflow
exec(sim_code, simModule.__dict__)
model_cls = simModule.__dict__[unit._name]
# can not use just function as it would get bounded to class
return BasicSimConstructor(model_cls, unit)
def generate_handshake_pipe_cntrl(parent: Unit, n: int, name_prefix: str, in_valid: RtlSignal, out_ready: RtlSignal):
"""
An utility that construct a pipe of registers to store the validity status of a register in the pipeline.
These registers are connected in pipeline and synchronized by handshake logic.
Clock enable signal for each stage in pipeline is also provided.
:ivar ~.n: number of stages
"""
clock_enables = []
valids = []
for i in range(n):
vld = parent._reg(f"{name_prefix:s}_{i:d}_valid", def_val=0)
valids.append(vld)
ce = parent._sig(f"{name_prefix:s}_{i:d}_clock_enable")
clock_enables.append(ce)
in_ready = out_ready
for i, (vld, ce) in enumerate(zip(valids, clock_enables)):
rd = rename_signal(parent,
Or(*[~_vld for _vld in valids[i + 1:]], out_ready),
f"{name_prefix:s}_{i:d}_ready")
if i == 0:
in_ready = rd | ~vld
prev_vld = in_valid
else:
prev_vld = valids[i - 1]
vld(apply_set_and_clear(vld, prev_vld, rd))
ce(~vld | (rd & prev_vld))
if n:
out_valid = valids[-1]
else:
out_valid = in_valid
return clock_enables, valids, in_ready, out_valid
def compileSimAndStart(self,
unit: Unit,
build_dir: Optional[str] = DEFAULT_BUILD_DIR,
unique_name: Optional[str] = None,
onAfterToRtl=None,
target_platform=DummySimPlatform()):
"""
Use this method if you did not used compileSim()
or SingleUnitSimTestCase to setup the simulator and DUT
"""
if unique_name is None:
unique_name = "%s__%s" % (self.getTestName(),
unit._getDefaultName())
self.compileSim(unit, build_dir, unique_name, onAfterToRtl,
target_platform)
self.u = unit
SimTestCase.setUp(self)
return self.u
def __init__(self, topUnit: Unit, name: str=None,
extra_files: List[str]=[],
serializer_cls=Vhdl2008Serializer,
target_platform=DummyPlatform()):
"""
:param topObj: :class:`hwt.synthesizer.unit.Unit` instance of top component
:param name: optional name of top
:param extra_files: list of extra HDL/constrain file names for files
which should be distributed in this IP-core
(\*.v - verilog, \*.sv,\*.svh -system verilog, \*.vhd - vhdl, \*.xdc - XDC)
:param serializer: serializer which specifies target HDL language
:param target_platform: specifies properties of target platform, like available resources, vendor, etc.
"""
if not name:
name = topUnit._getDefaultName()
super(IpPackager, self).__init__(
topUnit, name, extra_files)
self.serializer = serializer_cls
self.target_platform = target_platform
def __init__(self,
topUnit: Unit,
name: str = None,
extraVhdlFiles: List[str] = [],
extraVerilogFiles: List[str] = [],
serializer=VhdlSerializer,
targetPlatform=DummyPlatform()):
assert not topUnit._wasSynthetised()
self.topUnit = topUnit
self.serializer = serializer
self.targetPlatform = targetPlatform
if name:
self.name = name
else:
self.name = self.topUnit._getDefaultName()
self.hdlFiles = UniqList()
for f in extraVhdlFiles:
self.hdlFiles.append(f)
for f in extraVerilogFiles:
self.hdlFiles.append(f)
def _instantiateTimerTickLogic(parentUnit: Unit, timer: RtlSignal,
origMaxVal: Union[int, RtlSignal, HValue],
enableSig: Optional[RtlSignal],
rstSig: Optional[RtlSignal]) -> RtlSignal:
"""
Instantiate logic of this timer
:return: tick signal from this timer
"""
r = timer.cntrRegister
tick = r._eq(0)
if enableSig is None:
if rstSig is None:
If(tick, r(origMaxVal)).Else(r(r - 1))
else:
If(rstSig | tick, r(origMaxVal)).Else(r(r - 1))
else:
if rstSig is None:
If(enableSig, If(tick, r(origMaxVal)).Else(r(r - 1)))
else:
If(rstSig | (enableSig & tick),
r(origMaxVal)).Elif(enableSig, r(r - 1))
if enableSig is not None:
tick = (tick & enableSig)
if rstSig is not None:
tick = (tick & ~rstSig)
if timer.name:
# wrap tick in signal
s = parentUnit._sig(timer.name)
s(tick)
tick = s
return tick
def _config(self):
Unit._config(self)
def __init__(self, intfCls=AxiStream):
"""
:param hsIntfCls: class of interface which should be used as interface of this unit
"""
self.intfCls = intfCls
Unit.__init__(self)
def __init__(self, intfCls=AxiStream):
"""
:param hsIntfCls: class of interface which should be used as interface of this unit
"""
self.intfCls = intfCls
Unit.__init__(self)
def get_unique_name(cls, unit: Unit):
uniq_name = unit._getDefaultName()
return f"{cls.__name__:s}__{uniq_name:s}"
def get_unique_name(cls, unit: Unit):
return "%s__%s" % (cls.__name__, unit._getDefaultName())
def __init__(self, axiCls):
self.axiCls = axiCls
Unit.__init__(self)
def __init__(self):
Unit.__init__(self)
def __init__(self, intfCls: Type[MonitorIntf]):
self.intfCls = intfCls
Unit.__init__(self)
