def bench():
# Parameters
WIDTH = 16
i2s_ctrl_width = Signal(intbv(WIDTH))
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_l_tdata = Signal(intbv(0)[WIDTH:])
input_r_tdata = Signal(intbv(0)[WIDTH:])
input_tvalid = Signal(bool(0))
sck = Signal(bool(0))
ws = Signal(bool(0))
# Outputs
input_tready = Signal(bool(0))
sd = Signal(bool(0))
# Sources and sinks
input_source_queue = Queue()
input_source_pause = Signal(bool(0))
output_sink_queue = Queue()
input_source = axis_ep.AXIStreamSource(clk,
rst,
tdata=(input_l_tdata,
input_r_tdata),
tvalid=input_tvalid,
tready=input_tready,
fifo=input_source_queue,
pause=input_source_pause,
name='input_source')
i2s_ctrl = i2s_ep.I2SControl(clk,
rst,
sck=sck,
ws=ws,
width=i2s_ctrl_width,
prescale=2)
i2s_sink = i2s_ep.I2SSink(clk,
rst,
sck=sck,
ws=ws,
sd=sd,
width=WIDTH,
fifo=output_sink_queue,
name='sink')
# DUT
dut = dut_i2s_tx(clk, rst, current_test, input_l_tdata, input_r_tdata,
input_tvalid, input_tready, sck, ws, sd)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test ramp")
current_test.next = 1
y_l = list(range(0, 4096, 128))
y_r = list(range(4096 - 128, -128, -128))
y = list(zip(y_l, y_r))
input_source_queue.put(y)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
yield delay(3000)
lst = []
while not output_sink_queue.empty():
lst.append(output_sink_queue.get(False))
assert contains(y, lst)
yield delay(100)
yield clk.posedge
print("test 2: trailing zeros")
current_test.next = 2
i2s_ctrl_width.next = 24
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
y_l = list(range(0, 4096, 128))
y_r = list(range(4096 - 128, -128, -128))
y = list(zip(y_l, y_r))
input_source_queue.put(y)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
yield delay(5000)
lst = []
while not output_sink_queue.empty():
lst.append(output_sink_queue.get(False))
assert contains(y, lst)
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
prescale = Signal(intbv(0)[16:])
# Outputs
sck = Signal(bool(0))
ws = Signal(bool(0))
sck_check = Signal(bool(0))
ws_check = Signal(bool(0))
i2s_ctrl = i2s_ep.I2SControl(clk,
rst,
sck=sck_check,
ws=ws_check,
width=WIDTH,
prescale=prescale)
# DUT
dut = dut_i2s_ctrl(clk,
rst,
current_test,
sck,
ws,
prescale)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: no prescaler")
current_test.next = 1
for i in range(100):
print(sck, ws, sck_check, ws_check)
assert sck == sck_check
assert ws == ws_check
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 2: prescaler of 4")
current_test.next = 2
prescale.next = 4
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
for i in range(100):
print(sck, ws, sck_check, ws_check)
assert sck == sck_check
assert ws == ws_check
yield clk.posedge
yield delay(100)
raise StopSimulation
return instances()