def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) self.init = ila.bool(True) for index in range(self.thread_num): pc = self.model.getreg('pc_%d' % (index)) self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 for reg_name in ptx_declaration_shared: reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 for reg in ptx_declaration_diff: reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) self.init = self.init & (reg0 != reg1) & (reg0 <= 128) & ( reg0 >= 0) & (reg1 <= 128) & (reg1 >= 0) self.init = self.init & (self.en_log_register == 0) & (self.en_check_register == 0) bar_pred_map_obj = open('bar_pred_map', 'r') bar_pred_map = pickle.load(bar_pred_map_obj) bar_pred_map_obj.close() self.check_point = ila.bool(False) for pc in self.bar_list: bar_pred_list = bar_pred_map[pc] bar_pred = ila.bool(True) for bar_pred_name in bar_pred_list: bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (0)) bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1)) #self.condition = [] #for index in range(self.thread_num): # self.condition.append(self.pc_list[index] >= (self.pc_max)) #self.constrain = self.condition[0] #for index in range(1, len(self.condition)): # self.constrain = self.constrain & self.condition[index] self.imply = (self.check_register == self.log_register) & ( self.en_log_register == 1) & (self.en_check_register == 1) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def set_init(self): bar_spec = ptxILA.barSpec() self.a_is_bar = (self.opcode_a == bar_spec.BAR_OPCODE) #self.a_is_bar = (self.pc_a == 20) self.a_previous_bar = self.model.bit('a_previous_bar') self.model.set_next('a_previous_bar', self.a_is_bar) self.a_cross_bar_flag = self.model.bit('a_cross_bar_flag') self.model.set_next( 'a_cross_bar_flag', ila.ite((self.a_is_bar == ila.bool(False)) & (self.a_previous_bar == ila.bool(True)), ila.bool(True), self.a_cross_bar_flag)) self.b_is_bar = (self.opcode_b == bar_spec.BAR_OPCODE) self.b_come_to_bar_flag = self.model.bit('b_come_to_bar_flag') self.model.set_next( 'b_come_to_bar_flag', ila.ite(self.b_is_bar, ila.bool(True), self.b_come_to_bar_flag)) self.predicate_one = self.model.bit('predicate_one') self.model.set_next('predicate_one', (~self.a_cross_bar_flag) | (self.b_come_to_bar_flag)) self.model.set_init('a_previous_bar', self.model.bool(False)) self.model.set_init('a_cross_bar_flag', self.model.bool(False)) self.model.set_init('b_come_to_bar_flag', self.model.bool(False)) self.model.set_init('predicate_one', self.model.bool(True)) golden = ila.Abstraction('golden') g_prop = golden.bit('prop') golden.set_next('prop', golden.bool(True)) golden.set_init('prop', golden.bool(True)) ila.bmc(30, self.model, self.predicate_one, 1, golden, g_prop)
def generate_next_state(self, index): instruction_book_obj = open(FILE_DIR + 'instruction_book', 'r') instruction_book = instruction_book_obj.readlines() self.next_state_finished = [] pc_target = {} self.current_pc = 0 self.bar_sync_inst.append(ila.bool(False)) self.bar_aux_inst.append(ila.bool(False)) self.bar_arrive_inst.append(ila.bool(False)) for program_line in program: if len(program_line) < 2: if len(program_line) == 0: continue if program_line[0][-1] == ':': pc_target[program_line[0][:-1]] = self.current_pc else: self.current_pc += 4 print pc_target print self.current_pc self.current_pc = 0 for program_line in program: current_pc_in = self.current_pc self.perform_instruction(index, program_line, pc_target) for reg_name in ptx_declaration.keys(): if reg_name not in self.next_state_finished: reg = self.model.getreg(reg_name + '_%d' % (index)) self.model.set_next(reg_name + '_%d' % (index), reg) self.pc_max = self.current_pc
def create_data_race_element(self, access_set, pred_map, log): if log == True: suffix = 'log' index = 0 else: suffix = 'check' index = 1 self.log_clean = ila.bool(False) self.check_clean = ila.bool(False) for pc in self.bar_list: bar_pred_list = self.pred_map[pc] conj_bar_pred = self.pred_gen(index, bar_pred_list) self.log_clean = self.log_clean | ((self.pc_list[0] == pc) & (conj_bar_pred)) self.check_clean = self.check_clean | ((self.pc_list[0] == pc) & (conj_bar_pred)) for pc in access_set.keys(): reg_name = access_set[pc] operands = re.split('\+', reg_name) reg_len = 64 for i in range(len(operands)): operand = operands[i] if operand in ptx_declaration.keys(): op_reg_type = ptx_declaration[operand] op_reg_len = int(op_reg_type[2:]) if op_reg_len < reg_len: operands[i] = ila.sign_extend(self.model.getreg(operand + '_%d' % (index)), reg_len) else: operands[i] = self.model.getreg(operand + '_%d' % (index)) else: operands[i] = ila.const(int(operand), reg_len) access_reg_next = operands[0] for i in range(1, len(operands)): access_reg_next = access_reg_next + operands[i] en_access_reg_next = ila.const(0x1, 1) en_access_reg_clear = ila.const(0x0, 1) pred_list = self.pred_map[pc] conj_pred = self.pred_gen(index, pred_list) #if log: # self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.log_clean, ila.const(0x0, 1), en_access_reg))) #else: # self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.check_clean, ila.const(0x0, 1), en_access_reg))) if log: self.log_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1), access_reg_next, self.log_register_next) self.en_log_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_log_register_next) #self.log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.log_register_next), self.log_register_next) #self.en_log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_log_register_next), self.en_log_register_next) else: self.check_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1), access_reg_next, self.check_register_next) self.en_check_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_check_register_next) #self.check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.check_register_next), self.check_register_next) #self.en_check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_check_register_next), self.en_check_register_next) if log: self.en_log_register_next = ila.ite(self.log_clean, ila.const(0x0, 1), self.en_log_register_next) else: self.en_check_register_next = ila.ite(self.check_clean, ila.const(0x0, 1), self.en_check_register_next)
def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) self.init = ila.bool(True) for index in range(self.thread_num): pc = self.model.getreg('pc_%d' % (index)) self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 for reg_name in ptx_declaration_shared: reg_type = ptx_declaration[reg_name] reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) if int(reg_type[2:]) != instruction_format.LONG_REG_BITS: continue self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 for reg in ptx_declaration_diff: reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) self.init = self.init & (reg0 != reg1) & (reg0 <= 128) & ( reg0 >= 0) & (reg1 <= 128) & (reg1 >= 0) for reg in self.pred_registers: self.init = self.init & (reg == self.pred_one) #self.condition = [] #for index in range(self.thread_num): # self.condition.append(self.pc_list[index] >= (self.pc_max)) #self.constrain = self.condition[0] #for index in range(1, len(self.condition)): # self.constrain = self.constrain & self.condition[index] self.init = self.init & (self.bar_guarder_list[0] == ila.bool(True)) & (self.bar_guarder_list[1] == ila.bool(True)) self.bar_diverge_check = self.model.bit('bar_diverge_check') self.model.set_next( 'bar_diverge_check', ila.ite(self.bar_guarder_list[0] ^ self.bar_guarder_list[1], ila.bool(True), self.bar_diverge_check)) self.init = self.init & (self.bar_diverge_check == ila.bool(False))
def generate_next_state(self, index): instruction_book_obj = open('instruction_book', 'r') instruction_book = instruction_book_obj.readlines() self.next_state_finished = [] pc_target = {} self.current_pc = 0 self.bar_inst.append(ila.bool(False)) for program_line in program: if len(program_line) < 2: if len(program_line) == 0: continue if program_line[0][-1] == ':': pc_target[program_line[0][:-1]] = self.current_pc else: self.current_pc += 4 #print pc_target self.current_pc = 0 for program_line in program: current_pc_in = self.current_pc self.perform_instruction(index, program_line, pc_target) #if self.current_pc == current_pc_in: #Just to find if there's any instruction not in the instruction-book #print program_line for reg_name in ptx_declaration.keys(): if reg_name not in self.next_state_finished: #print reg_name reg = self.model.getreg(reg_name + '_%d' % (index)) self.model.set_next(reg_name + '_%d' % (index), reg) self.pc_max = self.current_pc
def isAccessCSR_Level(self,idxBits, level): expr = ila.bool(0) for name, CSR in self.CSRInfo.items(): if CSR.level != level: continue expr = expr | ( const(CSR.addr,12) == idxBits) return expr
def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) self.init = ila.bool(True) pc = self.model.getreg('pc') self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 for reg_name in ptx_declaration_shared: reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) operand_type = ptx_declaration[reg_name] operand_len = int(operand_type[2:]) if operand_len < 64: continue self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 for reg in ptx_declaration_diff: reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) self.init = self.init & (reg0 != reg1) & (reg0 <= 32) & ( reg0 >= 0) & (reg1 <= 32) & (reg1 >= 0) for reg in self.pred_registers: self.init = self.init & (reg == self.pred_one) self.init = self.init & (self.en_log_register == 0) & (self.en_check_register == 0) #self.condition = [] #for index in range(self.thread_num): # self.condition.append(self.pc_list[index] >= (self.pc_max)) #self.constrain = self.condition[0] #for index in range(1, len(self.condition)): # self.constrain = self.constrain & self.condition[index] tid0 = self.model.getreg('%tid.x_0') tid1 = self.model.getreg('%tid.x_1') self.imply = (self.check_register == self.log_register) & ( self.en_log_register == 1) & (self.en_check_register == 1) & ( (tid0 >> 5) != (tid1 >> 5)) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def pred_gen(self, index, pred_list): conj_pred = ila.bool(True) for pred in pred_list: if pred[0] == '-': pred_name = pred[1:] pred_cmp = self.pred_zero else: pred_name = pred pred_cmp = self.pred_one pred_reg = self.model.getreg(pred_name + '_%d' % (index)) conj_pred = conj_pred & (pred_reg == pred_cmp) return conj_pred
def aux_pc_target(self): self.pc_target = {} self.current_pc = 0 for i in range(self.thread_num): self.bar_inst.append(ila.bool(False)) for program_line in program: if len(program_line) < 2: if len(program_line) == 0: continue if program_line[0][-1] == ':': self.pc_target[program_line[0][:-1]] = self.current_pc else: self.current_pc += 4
def property_test2(self): bar_spec = ptxILA.barSpec() self.a_is_second_bar = (self.pc_a == 12 * instruction_format.MEM_BITS / 8) self.a_previous_is_second_bar = self.model.bit( 'a_previous_is_second_bar') self.model.set_next('a_previous_is_second_bar', self.a_is_second_bar) self.a_cross_second_bar_flag = self.model.bit( 'a_cross_second_bar_flag') self.model.set_next( 'a_cross_second_bar_flag', ila.ite((self.a_is_second_bar == ila.bool(False)) & (self.a_previous_is_second_bar == ila.bool(True)), ila.bool(True), self.a_cross_second_bar_flag)) self.b_is_second_bar = (self.pc_b == ila.const( 12 * instruction_format.MEM_BITS / 8, instruction_format.PC_BITS)) self.b_come_to_second_bar_flag = self.model.bit( 'b_come_to_second_bar_flag') self.model.set_next( 'b_come_to_second_bar_flag', ila.ite(self.b_is_second_bar, ila.bool(True), self.b_come_to_second_bar_flag)) self.predicate_two = self.model.bit('predicate_two') self.model.set_next('predicate_two', (~self.a_cross_second_bar_flag) | (self.b_come_to_second_bar_flag)) self.model.set_init('a_previous_is_second_bar', self.model.bool(False)) self.model.set_init('a_cross_second_bar_flag', self.model.bool(False)) self.model.set_init('b_come_to_second_bar_flag', self.model.bool(False)) self.model.set_init('predicate_two', self.model.bool(True)) golden = ila.Abstraction('golden') g_prop = golden.bit('prop') golden.set_next('prop', golden.bool(True)) golden.set_init('prop', golden.bool(True)) ila.bmc(10, self.model, self.predicate_two, 1, golden, g_prop)
def createBar(self): self.bar_state_next_list = [] self.bar_counter_enter_next_list = [] self.bar_counter_exit_next_list = [] self.bar_counter_max = self.thread_num for i in range(self.thread_num): self.bar_state_next_list.append(ila.ite(self.bar_arb == i, ila.ite(self.bar_inst[i] == ila.bool(True), ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, ila.const(self.bar_spec.BAR_INIT, self.bar_spec.BAR_STATE_BITS),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, ila.const(self.bar_spec.BAR_ENTER, self.bar_spec.BAR_STATE_BITS),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit != 0, self.bar_state_list[i],\ ila.ite(self.bar_counter_enter == (self.bar_counter_max - 1), ila.const(self.bar_spec.BAR_EXIT, self.bar_spec.BAR_STATE_BITS), ila.const(self.bar_spec.BAR_WAIT, self.bar_spec.BAR_STATE_BITS))),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, ila.ite(self.bar_counter_enter == self.bar_counter_max, ila.const(self.bar_spec.BAR_EXIT, self.bar_spec.BAR_STATE_BITS), self.bar_state_list[i]),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.const(self.bar_spec.BAR_FINISH, self.bar_spec.BAR_STATE_BITS), self.bar_state_list[i]))))), self.bar_state_list[i]), self.bar_state_list[i])) self.bar_counter_enter_next_list.append(ila.ite(self.bar_inst[i] == ila.bool(True), \ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, self.bar_counter_enter, \ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, self.bar_counter_enter,\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit == 0, self.bar_counter_enter + 1, self.bar_counter_enter),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, self.bar_counter_enter, \ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.ite(self.bar_counter_exit == 1, ila.const(0x0, self.bar_spec.BAR_COUNTER_ENTER_BITS), self.bar_counter_enter), self.bar_counter_enter))))), \ self.bar_counter_enter)) self.bar_counter_exit_next_list.append(ila.ite(self.bar_inst[i] == ila.bool(True),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, self.bar_counter_exit,\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, self.bar_counter_exit,\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit == 0, ila.ite(self.bar_counter_enter == (self.bar_counter_max - 1), ila.const(self.bar_counter_max, self.bar_spec.BAR_COUNTER_EXIT_BITS), self.bar_counter_exit), self.bar_counter_exit),\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, self.bar_counter_exit,\ ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.ite(self.bar_counter_exit != 0, self.bar_counter_exit - 1, self.bar_counter_exit - 1), self.bar_counter_exit))))),\ self.bar_counter_exit)) self.bar_counter_enter_next = self.bar_counter_enter self.bar_counter_exit_next = self.bar_counter_exit for i in range(self.thread_num): self.bar_counter_enter_next = ila.ite( self.bar_arb == i, self.bar_counter_enter_next_list[i], self.bar_counter_enter_next) self.bar_counter_exit_next = ila.ite( self.bar_arb == i, self.bar_counter_exit_next_list[i], self.bar_counter_exit_next)
def set_bar_guarder(self, index): self.bar_guarder_list.append(self.model.bit('bar_guarder_%d' % (index))) condition = ila.bool(False) for pc in self.bar_list: bar_preds = [] if pc in self.pred_map.keys(): bar_preds = self.pred_map[pc] bar_predicate = ila.bool(True) for bar_pred in bar_preds: if bar_pred[0] == '-': bar_pred_name = bar_pred[1:] bar_pred_cmp = self.pred_zero else: bar_pred_name = bar_pred bar_pred_cmp = self.pred_one bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (index)) bar_predicate = bar_predicate & (bar_pred_reg == bar_pred_cmp) condition = ((self.pc_list[index] == pc) & (bar_predicate)) | condition self.model.set_next( 'bar_guarder_%d' % (index), ila.ite(condition, ila.bool(True), ila.bool(False)))
def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) self.init = ila.bool(True) for index in range(self.thread_num): pc = self.model.getreg('pc_%d' %(index)) self.init = self.init & (pc == self.model.const(0x0, instruction_format.PC_BITS)) for reg_name in ptx_declaration_shared: reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) for reg in ptx_declaration_diff: reg0 = self.model.getreg(reg + '_%d' %(0)) reg1 = self.model.getreg(reg + '_%d' %(1)) self.init = self.init & (reg0 != reg1) & (reg0 <= 128) & (reg0 >= 0) & (reg1 <= 128) & (reg1 >= 0) for reg in self.en_log_registers: self.init = self.init & (reg == 0) for reg in self.en_check_registers: self.init = self.init & (reg == 0) #self.condition = [] #for index in range(self.thread_num): # self.condition.append(self.pc_list[index] >= (self.pc_max)) #self.constrain = self.condition[0] #for index in range(1, len(self.condition)): # self.constrain = self.constrain & self.condition[index] self.implied = self.model.bool(True) for i in range(len(self.log_registers)): for j in range(len(self.check_registers)): log_reg = self.log_registers[i] en_log_reg = self.en_log_registers[i] check_reg = self.check_registers[j] en_check_reg = self.en_check_registers[j] self.implied = self.implied & ((log_reg != check_reg) | (en_check_reg == 0) | (en_log_reg == 0)) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.imply = (self.implied) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next('predicate_bit', ila.ite(self.imply, self.predicate_bit, self.model.bool(False)))
return operand else: operand_int = int(operand_str) #print operand_int if operand_int < 0: operand_int = -operand_int operand_int = (1 << (op_len - 1)) - operand_int + (1 << (op_len - 1)) #print operand_int operand = self.model.const(operand_int, op_len) return operand ptx = ptxGPUModel() time_consumption = [] result = [] start = time.clock() a = ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), 100, ptx.init) end = time.clock() print end - start #for i in range(1, 30): # start = time.clock() # ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) # end = time.clock() # time_consumption.append(end - start) # r = ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) # result.append(r) #print time_consumption #print result #print ptx.model.bmcInit(ptx.predicate_bit == ila.bool(True), 28, True)
def create_data_race_element(self, access_set, pred_map, log): if log == True: suffix = 'log' index = 0 else: suffix = 'check' index = 1 bar_pred_map_obj = open('bar_pred_map', 'r') bar_pred_map = pickle.load(bar_pred_map_obj) bar_pred_map_obj.close() self.log_clean = ila.bool(False) self.check_clean = ila.bool(False) for pc in self.bar_list: bar_pred_list = bar_pred_map[pc] bar_pred = ila.bool(True) for bar_pred_name in bar_pred_list: bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (index)) bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1)) self.log_clean = self.log_clean | ((self.pc_list[0] == pc) & (bar_pred)) self.check_clean = self.check_clean | ((self.pc_list[0] == pc) & (bar_pred)) for pc in access_set.keys(): reg_name = access_set[pc] operands = re.split('\+', reg_name) reg_len = 64 for i in range(len(operands)): operand = operands[i] if operand in ptx_declaration.keys(): op_reg_type = ptx_declaration[operand] op_reg_len = int(op_reg_type[2:]) if op_reg_len < reg_len: operands[i] = ila.sign_extend( self.model.getreg(operand + '_%d' % (index)), reg_len) else: operands[i] = self.model.getreg(operand + '_%d' % (index)) else: operands[i] = ila.const(int(operand), reg_len) access_reg = self.model.reg(reg_name + '_%s_%d' % (suffix, pc), instruction_format.LONG_REG_BITS) if log: self.log_registers.append(access_reg) else: self.check_registers.append(access_reg) access_reg_next = operands[0] for i in range(1, len(operands)): access_reg_next = access_reg_next + operands[i] self.model.set_next( reg_name + '_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == (pc), access_reg_next, access_reg)) en_access_reg = self.model.reg( reg_name + '_en_%s_%d' % (suffix, pc), 1) if log: self.en_log_registers.append(en_access_reg) else: self.en_check_registers.append(en_access_reg) en_access_reg_next = ila.const(0x1, 1) en_access_reg_clear = ila.const(0x0, 1) pred_list = pred_map[pc] for pred in pred_list: pred_reg = self.model.getreg(pred + '_%d' % (index)) en_access_reg_next = ila.ite(pred_reg == ila.const(0x0, 1), en_access_reg_next, en_access_reg) if log: self.model.set_next( reg_name + '_en_%s_%d' % (suffix, pc), ila.ite( self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.log_clean, ila.const(0x0, 1), en_access_reg))) else: self.model.set_next( reg_name + '_en_%s_%d' % (suffix, pc), ila.ite( self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.check_clean, ila.const(0x0, 1), en_access_reg)))
operand_int = int(operand_str) print operand_int if operand_int < 0: operand_int = -operand_int operand_int = (1 << (op_len - 1)) - operand_int + (1 << (op_len - 1)) print operand_int operand = self.model.const(operand_int, op_len) return operand ptx = ptxGPUModel() time_consumption = [] result = [] #print ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), 30, ptx.init) ''' for i in range(1, 30): start = time.clock() ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) end = time.clock() time_consumption.append(end - start) r = ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) result.append(r) print time_consumption print result ''' print ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), 30, ptx.init) #print ptx.model.bmcInit(ptx.predicate_bit == ila.bool(True), 28, True)
def createStates(self): self.pc_list = [] #Two pc self.pc_next_list = [] #Two pc's next state function #self.imem_list = [] self.next_state_dict = {} #For next state function self.pred_registers = [] self.scalar_registers = [] self.long_scalar_registers = [] self.log_register = self.model.reg('log_register', instruction_format.LONG_REG_BITS) self.check_register = self.model.reg('check_register', instruction_format.LONG_REG_BITS) self.en_log_register = self.model.reg('en_log_register', 1) self.en_check_register = self.model.reg('en_check_register', 1) self.lsg_log_register = self.model.reg('lsg_log_register', 2) self.lsg_check_register = self.model.reg('lsg_check_register', 2) self.log_atom_flag_register = self.model.reg('log_atom_flag_register', 1) self.check_atom_flag_register = self.model.reg( 'check_atom_flag_register', 1) self.mflag_log_register = self.model.reg('mflag_log_register', 1) self.mflag_check_register = self.model.reg('mflag_check_register', 1) self.mguard_log_register = self.model.reg( 'mguard_log_register', instruction_format.LONG_REG_BITS) self.mguard_check_register = self.model.reg( 'mguard_check_register', instruction_format.LONG_REG_BITS) self.mutex_flag_list = [] self.mutex_guard_list = [] self.mutex_flag_next_list = [] self.mutex_guard_next_list = [] for i in range(2): self.mutex_flag_list.append( self.model.reg('mutex_flag_%d' % (i), 1)) self.mutex_guard_list.append( self.model.reg('mutex_guard_%d' % (i), instruction_format.LONG_REG_BITS)) self.mutex_flag_next_list.append(self.mutex_flag_list[i]) self.mutex_guard_next_list.append(self.mutex_guard_list[i]) #next state functions for monitors. self.mflag_log_register_next_cond = ila.bool(False) self.mflag_check_register_next_cond = ila.bool(False) self.mguard_log_register_next = self.mguard_log_register self.mguard_check_register_next = self.mguard_check_register self.log_register_next = self.log_register self.en_log_register_next = self.en_log_register self.lsg_log_register_next = self.lsg_log_register self.check_register_next = self.check_register self.en_check_register_next = self.en_check_register self.lsg_check_register_next = self.lsg_check_register self.log_atom_flag_register_next = self.log_atom_flag_register self.check_atom_flag_register_next = self.check_atom_flag_register self.arb_fun_list = [ self.model.fun('arb_fun_0', 1, []), self.model.fun('arb_fun_1', 1, []) ] self.arb_list = [ ila.appfun(self.arb_fun_list[0], []), ila.appfun(self.arb_fun_list[1], []) ] self.arb_data_fun_list = [ self.model.fun('arb_data_fun_0', instruction_format.LONG_REG_BITS, []), self.model.fun('arb_data_fun_1', instruction_format.LONG_REG_BITS, []) ] self.arb_data_list = [ ila.appfun(self.arb_data_fun_list[0]), ila.appfun(self.arb_data_fun_list[1]) ] self.bar_arrive_inst = [] self.bar_sync_inst = [] self.bar_aux_inst = [] self.bar_sync_list = [] self.bar_arrive_list = [] self.bar_aux_list = [] self.createPC() self.createRegs(0) self.createRegs(1) self.createConst() self.bar_state_list = [] self.generate_next_state(0) self.generate_next_state(1) self.createLog() self.createCheck() self.set_next_state() self.set_next_pc(0) self.set_next_pc(1)
def perform_instruction(self, index, program_line, pc_target): if len(program_line) < 2: return opcode = program_line[0] opcode_split = re.split('\.', opcode) opcode_name = opcode_split[0] if opcode_name != '@': op_preds = [] if self.current_pc in self.pred_map.keys(): op_preds = self.pred_map[self.current_pc] conj_pred = ila.bool(True) for op_pred in op_preds: if op_pred[0] == '-': op_pred_name = op_pred[1:] pred_cmp = self.pred_zero else: op_pred_name = op_pred pred_cmp = self.pred_one op_pred_reg = self.model.getreg(op_pred_name + '_%d' % (index)) conj_pred = conj_pred & (op_pred_reg == pred_cmp) self.next_state_finished.append(program_line[1]) if opcode_name == 'bar': op_len = 0 else: op_len = int(opcode_split[-1][1:]) src_list = [] for i in range(2, len(program_line)): src_str = program_line[i] src_components = re.split('\+', src_str) for i in range(len(src_components)): src_component = src_components[i] src_components[i] = self.aux_imm(src_component, index, op_len) src_sum = src_components[0] for i in range(1, len(src_components)): src_sum = src_sum + src_components[0] src_list.append(src_sum) dest = self.aux_dest(program_line[0], src_list, index) if not dest: self.current_pc += 4 return dest_str = program_line[1] dest = self.adjust_dest(index, dest, dest_str, op_len) ns = self.next_state_dict[dest_str + '_%d' % (index)] self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite( self.pc_list[index] == self.current_pc, ila.ite(conj_pred, dest, ns), ns) self.current_pc += 4 return else: op_preds = [] if self.current_pc in self.pred_map.keys(): op_preds = self.pred_map[self.current_pc] conj_pred0 = ila.bool(True) conj_pred1 = ila.bool(True) for op_pred in op_preds: if op_pred[0] == '-': op_pred_name = op_pred[1:] pred_cmp = self.pred_zero else: op_pred_name = op_pred pred_cmp = self.pred_one opcode_pred = self.model.getreg(op_pred_name + '_%d' % (0)) conj_pred0 = conj_pred0 & (opcode_pred == pred_cmp) opcode_pred = self.model.getreg(op_pred_name + '_%d' % (1)) conj_pred1 = conj_pred1 & (opcode_pred == pred_cmp) target = pc_target[program_line[3]] if self.current_pc < target: pc_jmp = ila.ite(conj_pred0 & conj_pred1, ila.const(target, instruction_format.PC_BITS), self.pc_list[index] + 4) self.pc_next_list[index] = ila.ite( self.pc_list[index] == self.current_pc, pc_jmp, self.pc_next_list[index]) else: pc_jmp = ila.ite(conj_pred0 | conj_pred1, ila.const(target, instruction_format.PC_BITS), self.pc_list[index] + 4) self.pc_next_list[index] = ila.ite( self.pc_list[index] == self.current_pc, pc_jmp, self.pc_next_list[index]) self.current_pc += 4
def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) #both threads start with pc = 0 for index in range(self.thread_num): pc = self.model.getreg('pc_%d' % (index)) self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 #Separate more than one memory array(continuous memory block). for reg_name in ptx_declaration_shared: reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) operand_type = ptx_declaration[reg_name] operand_len = int(operand_type[2:]) if operand_len < 64: continue self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 #limit thread numbers. thread_id_range_max = 128 thread_id_range_min = 0 for reg in ptx_declaration_diff: reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) self.init = self.init & (reg0 != reg1) & ( reg0 <= thread_id_range_max ) & (reg0 >= thread_id_range_min) & ( reg1 <= thread_id_range_max) & (reg1 >= thread_id_range_min) #All predicates initiated as one. for reg in self.pred_registers: self.init = self.init & (reg == self.pred_one) self.init = self.init & (self.en_log_register == 0) & (self.en_check_register == 0) bar_pred_map_obj = open('bar_pred_map', 'r') bar_pred_map = pickle.load(bar_pred_map_obj) bar_pred_map_obj.close() self.check_point = ila.bool(False) for pc in self.bar_list: bar_pred_list = bar_pred_map[pc] bar_pred = ila.bool(True) for bar_pred_name in bar_pred_list: bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (0)) bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1)) self.imply = (self.check_register == self.log_register) & ( self.en_log_register == 1) & (self.en_check_register == 1) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def create_data_race_element(self, access_set, log, lsg_update, atom): if log == True: suffix = 'log' index = 0 else: suffix = 'check' index = 1 self.log_clean = ila.bool(False) self.check_clean = ila.bool(False) for pc in self.bar_sync_list: self.log_clean = self.log_clean | ((self.pc_list[0] == pc) & (self.pc_list[1] == pc)) self.check_clean = self.check_clean | ((self.pc_list[0] == pc) & (self.pc_list[1] == pc)) ctaidx_0 = self.model.getreg('%ctaid.x_0') ctaidx_1 = self.model.getreg('%ctaid.x_1') ctaidy_0 = self.model.getreg('%ctaid.y_0') ctaidy_1 = self.model.getreg('%ctaid.y_1') self.log_clean = (self.log_clean) & ((ctaidx_0 == ctaidx_1) & (ctaidy_0 == ctaidy_1)) self.check_clean = (self.check_clean) & ((ctaidx_0 == ctaidx_1) & (ctaidy_0 == ctaidy_1)) for pc in access_set.keys(): reg_name = access_set[pc] operands = re.split('\+', reg_name) reg_len = 64 print operands for i in range(len(operands)): operand = operands[i] if operand in ptx_declaration.keys(): op_reg_type = ptx_declaration[operand] op_reg_len = int(op_reg_type[2:]) if op_reg_len < reg_len: operands[i] = ila.sign_extend( self.model.getreg(operand + '_%d' % (index)), reg_len) else: operands[i] = self.model.getreg(operand + '_%d' % (index)) else: operands[i] = self.aux_imm(operand, 0, reg_len) access_reg_next = operands[0] for i in range(1, len(operands)): access_reg_next = access_reg_next + operands[i] en_access_reg_next = ila.const(0x1, 1) en_access_reg_clear = ila.const(0x0, 1) if log: self.log_register_next = ila.ite( (self.pc_list[0] == pc) & (self.arb_list[index] == 1), access_reg_next, self.log_register_next) self.en_log_register_next = ila.ite( (self.pc_list[0] == pc) & (self.arb_list[index] == 1), en_access_reg_next, self.en_log_register_next) self.lsg_log_register_next = ila.ite( (self.pc_list[0] == pc) & (self.arb_list[index] == 1), lsg_update, self.lsg_log_register_next) self.mflag_log_register_next_cond = ( (self.arb_list[index] == 1) & (self.pc_list[0] == pc)) | self.mflag_log_register_next_cond if atom: self.log_atom_flag_register_next = ila.ite( (self.pc_list[0] == pc) & (self.arb_list[index] == 1), ila.const(0x1, 1), self.log_atom_flag_register_next) else: self.log_atom_flag_register_next = ila.ite( (self.pc_list[0] == pc) & (self.arb_list[index] == 1), ila.const(0x0, 1), self.log_atom_flag_register_next) else: self.check_register_next = ila.ite( (self.pc_list[1] == pc) & (self.arb_list[index] == 1), access_reg_next, self.check_register_next) self.en_check_register_next = ila.ite( (self.pc_list[1] == pc) & (self.arb_list[index] == 1), en_access_reg_next, self.en_check_register_next) self.lsg_check_register_next = ila.ite( (self.pc_list[1] == pc) & (self.arb_list[index] == 1), lsg_update, self.lsg_check_register_next) self.mflag_check_register_next_cond = ( (self.arb_list[index] == 1) & (self.pc_list[1] == pc)) | self.mflag_check_register_next_cond if atom: self.check_atom_flag_register_next = ila.ite( (self.pc_list[1] == pc) & (self.arb_list[index] == 1), ila.const(0x1, 1), self.check_atom_flag_register_next) else: self.check_atom_flag_register_next = ila.ite( (self.pc_list[1] == pc) & (self.arb_list[index] == 1), ila.const(0x0, 1), self.check_atom_flag_register_next) if log: self.en_log_register_next = ila.ite(self.log_clean, ila.const(0x0, 1), self.en_log_register_next) else: self.en_check_register_next = ila.ite(self.check_clean, ila.const(0x0, 1), self.en_check_register_next)
check_reg = self.check_registers[j] en_check_reg = self.en_check_registers[j] self.implied = self.implied & ((log_reg != check_reg) | (en_check_reg == 0) | (en_log_reg == 0)) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.imply = (~(self.constrain)) | (self.implied) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.cond = self.cond & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.predicate_bit, self.model.bool(False))) def aux_imm(self, operand_str, index): if operand_str in ptx_declaration.keys(): operand = self.model.getreg(operand_str + '_%d' % (index)) operand_type = ptx_declaration[operand_str] operand_length = int(operand_type[2:]) else: operand_length = instruction_format.REG_BITS operand = self.model.const(int(operand_str), operand_length) return (operand, operand_length) ptx = ptxGPUModel() print ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), 20, ptx.cond) #print ptx.model.bmcInit(ptx.predicate_bit == ila.bool(True), 28, True)
def add_assumptions(self): ptx_declaration_diff_obj = open(TMP_DIR + 'diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open(TMP_DIR + 'shared_readonly_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) ptx_parameter_regs_obj = open(TMP_DIR + 'parameter_regs', 'r') ptx_parameter_regs = pickle.load(ptx_parameter_regs_obj) ptx_buildin_regs_obj = open(TMP_DIR + 'buildin_regs', 'r') ptx_buildin_regs = pickle.load(ptx_buildin_regs_obj) ptx_shared_read_only_range_regs_obj = open( TMP_DIR + 'shared_read_only_range_regs', 'r') ptx_shared_read_only_range_regs = pickle.load( ptx_shared_read_only_range_regs_obj) ptx_zero_starter_obj = open(TMP_DIR + 'zero_starter', 'r') ptx_zero_starter = pickle.load(ptx_zero_starter_obj) self.init = ila.bool(True) pc = self.model.getreg('pc_0') self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) pc = self.model.getreg('pc_1') self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 for reg_name in ptx_declaration_shared: reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) operand_type = ptx_declaration[reg_name] operand_len = int(operand_type[2:]) if operand_len < 64: self.init_max = self.model.const( i, instruction_format.REG_BITS) << 27 self.init_range = self.model.const( 1, instruction_format.REG_BITS) << 26 self.init = self.init & (reg0 == (self.init_max - self.init_range)) i += 1 continue self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 == (self.init_max - self.init_range)) i += 1 self.diff = ila.bool(False) self.diff_range = ila.bool(True) for reg in ptx_declaration_diff.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_declaration_diff[reg] self.diff = self.diff | (reg0 != reg1) self.diff_range = self.diff_range & (reg0 < v) & (reg1 < v) & ( reg0 >= 0) & (reg1 >= 0) self.init = self.init & self.diff_range & self.diff for reg in ptx_parameter_regs.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_parameter_regs[reg] self.init = self.init & (reg0 == v) & (reg1 == v) for reg in ptx_buildin_regs.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_buildin_regs[reg] self.init = self.init & (reg0 == v) & (reg1 == v) for reg in ptx_shared_read_only_range_regs.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_shared_read_only_range_regs[reg] self.init = self.init & (reg0 > 0) & (reg0 < v) & (reg0 == reg1) for reg in ptx_zero_starter: reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) self.init = self.init & (reg0 == 0) & (reg1 == 0) for reg in self.pred_registers: self.init = self.init & (reg == self.pred_one) self.init = self.init & (self.en_log_register == 0) & ( self.en_check_register == 0) & (self.log_atom_flag_register == 0) & (self.check_atom_flag_register == 0) self.init = self.init & (self.mutex_flag_list[0] == 0) & ( self.mutex_flag_list[1] == 0) & (self.mflag_log_register == 0) & ( self.mflag_check_register == 0) tidx0 = self.model.getreg('%tid.x_0') tidx1 = self.model.getreg('%tid.x_1') tidy0 = self.model.getreg('%tid.y_0') tidy1 = self.model.getreg('%tid.y_1') tidz0 = self.model.getreg('%tid.z_0') tidz1 = self.model.getreg('%tid.z_1') ctaidx0 = self.model.getreg('%ctaid.x_0') ctaidx1 = self.model.getreg('%ctaid.x_1') ctaidy0 = self.model.getreg('%ctaid.y_0') ctaidy1 = self.model.getreg('%ctaid.y_1') ctaidz0 = self.model.getreg('%ctaid.z_0') ctaidz1 = self.model.getreg('%ctaid.z_1') # Imply with no warp self.imply = (~( (self.log_atom_flag_register == 1) & (self.check_atom_flag_register == 1))) & ( self.check_register == self.log_register ) & (self.en_log_register == 1) & (self.en_check_register == 1) & ( ((self.lsg_log_register == 2) & (self.lsg_check_register == 2)) | ((self.lsg_log_register == 1) & (self.lsg_check_register == 1) & (ctaidx0 == ctaidx1) & (ctaidy0 == ctaidy1) & (ctaidz0 == ctaidz1)) ) #& (~((ctaidx0 == ctaidx1) & ((tid0 >> 5) == (tid1 >> 5)))) #& (ctaidx0 == ctaidx1) & (ctaidy0 == ctaidy1))) #& ((tid0 >> 5) != (tid1 >> 5)) # Imply with warp # self.imply = (self.imply) | ((self.log_register_next != self.log_register) & (self.check_register_next != self.check_register) & (self.check_register_next == self.log_register_next) & (self.en_log_register_next == 1) & (self.en_check_register_next == 1) & (((self.lsg_log_register_next == 2) & (self.lsg_check_register_next == 2)) | ((self.lsg_log_register_next == 1) & (self.lsg_check_register_next == 1))) & (ctaidx0 == ctaidx1) & ((tid0 >> 5) == (tid1 >> 5))) #& (ctaidx0 == ctaidx1) & (ctaidy0 == ctaidy1))) #& ((tid0 >> 5) != (tid1 >> 5)) # Imply with rel acq self.imply = self.imply & (~( (self.mflag_log_register == 1) & (self.mflag_check_register == 1) & (self.mguard_log_register == self.mguard_check_register))) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def add_assumptions(self): ptx_declaration_diff_obj = open('diff_read_only_regs', 'r') ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj) ptx_declaration_shared_obj = open('shared_read_only_regs', 'r') ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj) ptx_parameter_regs_obj = open('parameter_regs', 'r') ptx_parameter_regs = pickle.load(ptx_parameter_regs_obj) self.init = ila.bool(True) pc = self.model.getreg('pc_0') self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) pc = self.model.getreg('pc_1') self.init = self.init & (pc == self.model.const( 0x0, instruction_format.PC_BITS)) i = 1 for reg_name in ptx_declaration_shared: #TODO: change this in future. #if reg_name[0] == '%': # continue reg0 = self.model.getreg(reg_name + '_%d' % (0)) reg1 = self.model.getreg(reg_name + '_%d' % (1)) self.init = self.init & (reg0 == reg1) operand_type = ptx_declaration[reg_name] operand_len = int(operand_type[2:]) if operand_len < 64: self.init_max = self.model.const( i, instruction_format.REG_BITS) << 27 self.init_range = self.model.const( 1, instruction_format.REG_BITS) << 26 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 continue self.init_max = self.model.const( i, instruction_format.LONG_REG_BITS) << 59 self.init_range = self.model.const( 1, instruction_format.LONG_REG_BITS) << 58 self.init = self.init & (reg0 < self.init_max) & ( reg0 > (self.init_max - self.init_range)) i += 1 self.diff = ila.bool(False) self.diff_range = ila.bool(True) for reg in ptx_declaration_diff.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_declaration_diff[reg] self.diff = self.diff | (reg0 != reg1) self.diff_range = self.diff_range & (reg0 < v) & (reg1 < v) & ( reg0 >= 0) & (reg1 >= 0) #self.init = self.init & (reg0 != reg1) & (reg0 < 64) & (reg0 >= 0) & (reg1 < 64) & (reg1 >= 0) self.init = self.init & self.diff_range & self.diff for reg in ptx_parameter_regs.keys(): reg0 = self.model.getreg(reg + '_%d' % (0)) reg1 = self.model.getreg(reg + '_%d' % (1)) v = ptx_parameter_regs[reg] self.init = self.init & (reg0 == v) & (reg1 == v) for reg in self.pred_registers: self.init = self.init & (reg == self.pred_one) self.init = self.init & (self.en_log_register == 0) & (self.en_check_register == 0) #self.condition = [] #for index in range(self.thread_num): # self.condition.append(self.pc_list[index] >= (self.pc_max)) #self.constrain = self.condition[0] #for index in range(1, len(self.condition)): # self.constrain = self.constrain & self.condition[index] tid0 = self.model.getreg('%tid.x_0') tid1 = self.model.getreg('%tid.x_1') #ctaidx0 = self.model.getreg('%ctaid.x_0') #ctaidx1 = self.model.getreg('%ctaid.x_1') #ctaidy0 = self.model.getreg('%ctaid.y_0') #ctaidy1 = self.model.getreg('%ctaid.y_1') #self.imply = (self.check_register == self.log_register) & (self.en_log_register == 1) & (self.en_check_register == 1) & (((self.lsg_log_register == 2) & (self.lsg_check_register == 2)) | ((self.lsg_log_register == 1) & (self.lsg_check_register == 1))) #& (ctaidx0 == ctaidx1) & (ctaidy0 == ctaidy1))) #& ((tid0 >> 5) != (tid1 >> 5)) self.imply = (self.pc_list[0] == 404) # self.implied = self.implied & (self.mem_list[0] == self.mem_list[1]) self.predicate_bit = self.model.bit('predicate_bit') #self.model.set_init('predicate_bit', self.model.bool(True)) self.init = self.init & (self.predicate_bit == self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def create_data_race_element(self, log): if log == True: index = 0 bar_pass = ((self.is_bar_list[0]) & (self.is_bar_list[1])) mem_lsg_type = self.fetch_inst_list[index][( instruction_format.MEM_LSG_TOP - 1):instruction_format.MEM_LSG_BOT] is_log_mem_access = (self.is_ld_list[index]) | ( self.is_st_list[index]) src0_long_flag = self.src0_long_list[index] sreg0_index = self.sreg0_index_list[index] sreg0_scalar_reg = self.get_scalar_reg(sreg0_index) sreg0_long_scalar_reg = self.get_long_scalar_reg(sreg0_index) sreg0 = ila.ite( src0_long_flag, sreg0_long_scalar_reg[(instruction_format.DMEM_BITS - 1):0], sreg0_scalar_reg) imm_addr = ila.sign_extend(self.imm_list[index], instruction_format.DMEM_BITS) mem_address = sreg0 + imm_addr #Assume ld/st 32bits address log_register_next = ila.ite( is_log_mem_access, ila.ite(self.arb_list[index] == 1, mem_address, self.log_register), self.log_register) en_log_register_next = ila.ite( bar_pass, ila.bool(False), ila.ite( is_log_mem_access, ila.ite(self.arb_list[index] == 1, ila.bool(True), en_log_register), en_log_register)) lsg_log_register_next = ila.ite( is_log_mem_access, ila.ite(self.arb_list[index] == 1, mem_lsg_type, lsg_log_register), lsg_log_register) self.model.set_next('log_regiseter', log_register_next) self.model.set_next('en_log_register', en_log_register_next) self.model.set_next('lsg_log_register', lsg_log_register_next) else: index = 1 bar_pass = ((self.is_bar_list[0]) & (self.is_bar_list[1])) mem_lsg_type = self.fetch_inst_list[index][( instruction_format.MEM_LSG_TOP - 1):instruction_format.MEM_LSG_BOT] is_check_mem_access = (self.is_st_list[index]) src0_long_flag = self.src0_long_list[index] sreg0_index = self.sreg0_index_list[index] sreg0_scalar_reg = self.get_scalar_reg(sreg0_index) sreg0_long_scalar_reg = self.get_long_scalar_reg(sreg0_index) sreg0 = ila.ite( src0_long_flag, sreg0_long_scalar_reg[(instruction_format.DMEM_BITS - 1):0], sreg0_scalar_reg) imm_addr = ila.sign_extend(self.imm_list[index], instruction_format.DMEM_BITS) mem_address = sreg0 + imm_addr #Assume ld/st 32bits address check_register_next = ila.ite( is_check_mem_access, ila.ite(self.arb_list[index] == 1, mem_address, self.check_register), self.check_register) en_check_register_next = ila.ite( bar_pass, ila.bool(False), ila.ite( is_check_mem_access, ila.ite(self.arb_list[index] == 1, ila.bool(True), en_check_register), en_check_register)) lsg_check_register_next = ila.ite( is_check_mem_access, ila.ite(self.arb_list[index] == 1, mem_lsg_type, lsg_check_register), lsg_check_register) self.model.set_next('check_register', check_register_next) self.model.set_next('en_check_register', en_check_register_next) self.model.set_next('lsg_check_register'.lsg_check_register_next)
self.constrain = self.constrain & self.flag_list[1] & self.flag_list[ 2] & (self.flag_list[3]) & (~self.flag_list[4]) for index in range(len(self.condition)): self.constrain = self.constrain & self.condition[index] self.imply_rega = self.model.getreg('s6_0') self.imply_regb = self.model.getreg('s8_0') self.imply_result_addra = self.model.getreg('s5_0') self.imply_result_addrb = self.model.getreg('s7_0') self.imply_result = self.mem[self.imply_result_addra[ (instruction_format.MEM_ADDRESS_BITS - 1):0]] + self.mem[self.imply_result_addrb[ (instruction_format.MEM_ADDRESS_BITS - 1):0]] self.imply = (~(self.constrain)) | ((self.imply_rega + self.imply_regb) == self.imply_result) print self.imply self.predicate_bit = self.model.bit('predicate_bit') self.model.set_init('predicate_bit', self.model.bool(True)) self.model.set_next( 'predicate_bit', ila.ite(self.imply, self.predicate_bit, self.model.bool(False))) ptx = ptxGPUModel() golden_model = ila.Abstraction('golden') g_prop = golden_model.bit('prop') golden_model.set_init('prop', golden_model.bool(True)) golden_model.set_next('prop', golden_model.bool(True)) #print ila.bmc(15, ptx.model, ptx.predicate_bit, 10, golden_model, g_prop) print ptx.model.bmcInit(ptx.predicate_bit == ila.bool(True), 30, True)
def false(): return ila.bool(0)
return operand[(op_len - 1):0] else: return operand else: operand_int = int(operand_str) #print operand_int if operand_int < 0: operand_int = -operand_int operand_int = (1 << (op_len - 1)) - operand_int + (1 << (op_len - 1)) #print operand_int operand = self.model.const(operand_int, op_len) return operand ptx = ptxGPUModel() time_consumption = [] result = [] print ptx.model.bmcCond(ptx.bar_diverge_check == ila.bool(False), 40, ptx.init) #for i in range(1, 30): # start = time.clock() # ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) # end = time.clock() # time_consumption.append(end - start) # r = ptx.model.bmcCond(ptx.predicate_bit == ila.bool(True), i, ptx.init) # result.append(r) #print time_consumption #print result #print ptx.model.bmcInit(ptx.predicate_bit == ila.bool(True), 28, True)