def testAmbiguitySet(self):
"""Checks that an error is raised if an ambiguity exists between a set of instructions."""
isaVar = isa.ISA()
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('opc', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('shift_amm', 5), ('shift_op', 2), ('zero', 1), ('rm', 4)])
dataProc_imm_shift.setBitfield('opc', [1, 0, None])
ls_immOff = isa.MachineCode([('cond', 4), ('opcode', 2), ('p', 2), ('u', 1), ('b', 1), ('w', 1), ('l', 1), ('rn', 4), ('rd', 4), ('immediate', 12)])
ls_immOff.setBitfield('opcode', [1, 0])
ls_multiple = isa.MachineCode([('cond', 4), ('opcode', 3), ('p', 1), ('u', 1), ('s', 1), ('w', 1), ('l', 1), ('rn', 4), ('reg_list', 16)])
ls_multiple.setBitfield('opcode', [1, 0, 0])
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift, {'opcode': [None, None, None, None]}, 'TODO')
secondInstr = isa.Instruction('SECOND', False)
secondInstr .setMachineCode(ls_immOff)
thirdInstr = isa.Instruction('THIRD', False)
thirdInstr .setMachineCode(ls_multiple)
isaVar.addInstruction(adc_shift_imm_Instr)
isaVar.addInstruction(secondInstr)
isaVar.addInstruction(thirdInstr)
# Run checks.
isaVar.computeCoding()
error = False
try:
isaVar.checkCoding()
except:
error = True
self.assert_(error)
def testComputeCoding1(self):
"""Checks that everything is ok if no ambiguity exists in the instruction encoding"""
isaVar = isa.ISA()
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3),
('opcode', 4), ('s', 1),
('rn', 4), ('rd', 4),
('shift_amm', 5),
('shift_op', 2), ('zero', 1),
('rm', 4)])
dataProc_reg_shift = isa.MachineCode([('cond', 4), ('zero', 3),
('opcode', 4), ('s', 1),
('rn', 4), ('rd', 4), ('rs', 4),
('zero', 1), ('shift_op', 2),
('one', 1), ('rm', 4)])
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift,
{'opcode': [0, 1, 0, 1]}, 'TODO')
adc_shift_reg_Instr = isa.Instruction('ADC_sr', True)
adc_shift_reg_Instr.setMachineCode(dataProc_reg_shift,
{'opcode': [0, 1, 0, 1]}, 'TODO')
isaVar.addInstruction(adc_shift_imm_Instr)
isaVar.addInstruction(adc_shift_reg_Instr)
# Now we can compute the checks
isaVar.computeCoding()
self.assertEqual([None for i in range(0, 4)] + [0, 0, 0, 0, 1, 0, 1] +
[None for i in range(0, 16)] + [0] +
[None
for i in range(0, 4)], adc_shift_imm_Instr.bitstring)
self.assertEqual([None for i in range(0, 4)] + [0, 0, 0, 0, 1, 0, 1] +
[None for i in range(0, 13)] + [0] + [None, None] +
[1] + [None for i in range(0, 4)],
adc_shift_reg_Instr.bitstring)
def testOk(self):
"""Checks that everything is ok if no ambiguity exists in the instruction encoding"""
isaVar = isa.ISA()
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3),
('opcode', 4), ('s', 1),
('rn', 4), ('rd', 4),
('shift_amm', 5),
('shift_op', 2), ('zero', 1),
('rm', 4)])
ls_immOff = isa.MachineCode([('cond', 4), ('opcode', 3), ('p', 1),
('u', 1), ('b', 1), ('w', 1), ('l', 1),
('rn', 4), ('rd', 4), ('immediate', 12)])
ls_immOff.setBitfield('opcode', [0, 1, 0])
ls_multiple = isa.MachineCode([('cond', 4), ('opcode', 3), ('p', 1),
('u', 1), ('s', 1), ('w', 1), ('l', 1),
('rn', 4), ('reg_list', 16)])
ls_multiple.setBitfield('opcode', [1, 0, 0])
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift,
{'opcode': [0, 1, 0, 1]}, 'TODO')
secondInstr = isa.Instruction('SECOND', False)
secondInstr.setMachineCode(ls_immOff)
thirdInstr = isa.Instruction('THIRD', False)
thirdInstr.setMachineCode(ls_multiple)
isaVar.addInstruction(adc_shift_imm_Instr)
isaVar.addInstruction(secondInstr)
isaVar.addInstruction(thirdInstr)
# Now we can compute the checks
isaVar.computeCoding()
isaVar.checkCoding()
def testOk(self):
"""Tests that no problems are signaled in case all registers are valid
and there are no references to nonexistent registers."""
proc = processor.Processor('test', '0')
regBank = processor.RegisterBank('RB', 30, 32)
proc.addRegBank(regBank)
cpsrBitMask = {'N': (31, 31), 'Z': (30, 30), 'C': (29, 29), 'V': (28, 28), 'I': (7, 7), 'F': (6, 6), 'mode': (0, 4)}
cpsr = processor.Register('CPSR', 32, cpsrBitMask)
cpsr.setDefaultValue(0x000000D3)
proc.addRegister(cpsr)
regs = processor.AliasRegBank('REGS', 16, 'RB[0-15]')
proc.addAliasRegBank(regs)
abi = processor.ABI('REGS[0]', 'REGS[0-3]', 'RB[15]')
abi.addVarRegsCorrespondence({'REGS[0-15]': (0, 15), 'CPSR': (25, 25)})
proc.setABI(abi)
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('shift_amm', 5), ('shift_op', 2), ('zero', 1), ('rm', 4)])
dataProc_imm_shift.setVarField('rn', ('REGS', 0))
dataProc_imm_shift.setVarField('rd', ('RB', 0))
dataProc_imm_shift.setVarField('rm', ('REGS', 0))
isaVar = isa.ISA()
proc.setISA(isaVar)
opCode = cxx_writer.Code('')
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift, {'opcode': [0, 1, 0, 1]}, 'TODO')
isaVar.addInstruction(adc_shift_imm_Instr)
# Call the check functions: They raise exceptions if there is a problem.
proc.checkAliases()
proc.checkABI()
proc.isa.checkRegisters(processor.extractRegInterval, proc.isRegExisting)
def testABIReg(self):
"""Tests that an exception is raised in case the ABI refers to
a non existing register"""
proc = processor.Processor('test', '0')
regBank = processor.RegisterBank('RB', 30, 32)
proc.addRegBank(regBank)
cpsrBitMask = {
'N': (31, 31),
'Z': (30, 30),
'C': (29, 29),
'V': (28, 28),
'I': (7, 7),
'F': (6, 6),
'mode': (0, 4)
}
cpsr = processor.Register('CPSR', 32, cpsrBitMask)
cpsr.setDefaultValue(0x000000D3)
proc.addRegister(cpsr)
regs = processor.AliasRegBank('REGS', 16, 'RB[0-15]')
proc.addAliasRegBank(regs)
PC = processor.AliasRegister('PC', 'REGS[15]')
proc.addAliasReg(PC)
abi = processor.ABI('REGS[0]', 'REGS[0-3]', 'RB[15]')
abi.addVarRegsCorrespondence({
'REGS[0-15]': (0, 15),
'UNEXISTING': (25, 25)
})
proc.setABI(abi)
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3),
('opcode', 4), ('s', 1),
('rn', 4), ('rd', 4),
('shift_amm', 5),
('shift_op', 2), ('zero', 1),
('rm', 4)])
dataProc_imm_shift.setVarField('rn', ('REGS', 0))
dataProc_imm_shift.setVarField('rd', ('RB', 0))
dataProc_imm_shift.setVarField('rm', ('REGS', 0))
isaVar = isa.ISA()
proc.setISA(isaVar)
opCode = cxx_writer.writer_code.Code('')
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift,
{'opcode': [0, 1, 0, 1]}, 'TODO')
isaVar.addInstruction(adc_shift_imm_Instr)
# The I call the check functions: they raise exceptions in case
# there is a problem
foundError = False
proc.isa.checkRegisters(processor.extractRegInterval,
proc.isRegExisting)
proc.checkAliases()
try:
proc.checkABI()
except:
foundError = True
self.assert_(foundError)
def testComputeCoding2(self):
"""Checks that everything is ok if the instruction encoding is not
ambiguous."""
isaVar = isa.ISA()
dataProc_imm_shift = isa.MachineCode([('cond', 4), ('one', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('shift_amm', 5), ('shift_op', 2), ('one', 1), ('rm', 4)])
adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift, {'opcode': [0, 1, 0, 1]}, 'TODO')
isaVar.addInstruction(adc_shift_imm_Instr)
# Run checks.
isaVar.computeCoding()
self.assertEqual([None for i in range(0, 4)] + [1, 1, 1, 0, 1, 0, 1] + [None for i in range(0, 16)] + [1] + [None for i in range(0, 4)], adc_shift_imm_Instr.bitstring)
def fetch_and_decode(self, asm, machineCode):
self.instructions = []
for line in asm:
self.instructions.append(isa.Instruction(line, machineCode))
rowCount = len(self.instructions) + 1
colCount = len(self.instructions) * 4
if len(self.instructions) == 1:
colCount = 7
self.tableWidget.setRowCount(rowCount)
self.tableWidget.setColumnCount(colCount)
rowHeaders = ["Instructions:"]
colHeaders = ["mem address:", "instr №"]
i = 1
while i <= colCount:
colHeaders.append("CC" + str(i))
i = i + 1
self.tableWidget.setHorizontalHeaderLabels(colHeaders)
row = 1
for instr in self.instructions:
self.tableWidget.setItem(
row, 0, QtWidgets.QTableWidgetItem(str(instr.NPC)))
if machineCode:
rowHeaders.append(instr.decodedInstr)
self.tableWidget.setItem(
row, 1, QtWidgets.QTableWidgetItem("I" + str(row - 1)))
else:
rowHeaders.append(instr.fullInstr)
self.tableWidget.setItem(
row, 1, QtWidgets.QTableWidgetItem("I" + str(row - 1)))
row = row + 1
self.tableWidget.setVerticalHeaderLabels(rowHeaders)
self.tableWidget.setHorizontalHeaderLabels(colHeaders)
