def openPort(self):
self.portId = os.open(self.devfile, os.O_RDONLY | os.O_NONBLOCK)
if self.portId == 0:
Bc.printError("Could not open " + devfile + " for read")
return False
else:
return True
def __init__(self, ip):
resource = environ.get('DP800_IP', 'TCPIP0::' + str(ip) + '::INSTR')
self.rigol = RigolDP800(resource, 0)
self.rigol.open()
Bcolors.printPassed("Rigol DP832A - Connected to device on " + str(ip))
self.rigol.beeperOff()
self.rigol.outputOffAll()
def stop(self):
Bcolors.printInfo("Rigol DP832A - Stop and close connection")
self.rigol.outputOffAll()
# return to LOCAL mode
self.rigol.setLocal()
self.rigol.close()
def write_to_mem(addr, data, writePort):
Bcolors.printInfo("Write " + str(data) + " to addr " + str(addr))
instruction_addr = (instructions.spi_write << 29) | addr
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(addr))
writePort.sendInt(instruction_addr)
instruction_data = (instructions.spi_write << 29) | data
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(data))
writePort.sendInt(instruction_data)
def reset(readPort, writePort):
Bcolors.printInfo("Resetting ... ")
toggle_reset(writePort)
time.sleep(0.1)
toggle_reset(writePort)
#before starting measurement, clearing the values from the FIFO
clear_results(readPort)
def __init__(self, devfile, width):
if width%8 != 0:
Bc.printError(" width: " + str(width) + " is no multiple of 8 bits (1 byte)")
else:
self.devfile = devfile
self.width = width
self.nbBytes = width/8
self.portId = 0
ReadPort.readPortCount += 1
def set_voltage(self, voltage, channel=1):
Bcolors.printInfo("Rigol DP832A - Setting voltage on channel " +
str(channel) + " to " + str(voltage) + "V")
if voltage <= 1 or channel == 2:
self.rigol.setVoltage(voltage, channel)
else:
Bcolors.printInfo("Rigol DP832A - Voltage to high on channel " +
str(channel) + " for voltage " + str(voltage) +
"V")
self.turn_off_all()
exit()
def setFrequency(self,frequency,writePort,verbose=False):
## Set extra 8 divisor on or off +
#if frequency < 5:
# extraDivOn = True
#else:
# extraDivOn = False
#
##reset mmcm for configuration + set divider on/off
#self.map.seek(0x0000,os.SEEK_SET)
#if extraDivOn:
# self.map.write_byte(chr(0x03))
#else:
# self.map.write_byte(chr(0x01))
#
## Set power register
#self.map.seek(0x10A0,os.SEEK_SET)
#self.map.write(struct.pack("I",0x0000FFFF))
# Find nearest frequency, this frequency will be used
#if extraDivOn:
# exactFrequency = self.findNearestFrequency(frequency*8,verbose)
#else:
# exactFrequency = self.findNearestFrequency(frequency,verbose)
instruction = (instructions.chip_setclk << 29) | (0x28 << 16) | (0xFFFF)
writePort.sendInt(instruction)
exactFrequency = self.findNearestFrequency(frequency,verbose)
with open(cnst.PROJDIR + "/python/lookup_data/freq_" + "%.2f" % exactFrequency + ".csv","r") as lookUpFile:
for i, line in enumerate(lookUpFile):
if i != 0:
regName, fakeAddr, value = line.split(",")
if verbose:
Bcolors.printInfo(regName + "address:" + str(Clock.drpAddressMap[regName[1:-1]]) + " value: " + hex(int(value,16)))
addr = Clock.drpAddressMap[regName[1:-1]]
instruction = (instructions.chip_setclk << 29) | (addr << 16) | int(value,16)
writePort.sendInt(instruction)
#self.map.seek(0x1000 + 4*Clock.drpAddressMap[regName[1:-1]],os.SEEK_SET)
#self.map.write(struct.pack("I",int(value,16)))
#time.sleep(0.001)
#if verbose:
# self.printDRPRegisters()
#self.map.seek(0x0000,os.SEEK_SET)
#if extraDivOn:
# self.map.write_byte(chr(0x02))
# return exactFrequency/8
#else:
# self.map.write_byte(chr(0x00))
# return exactFrequency
return exactFrequency
def openPort(self):
self.portId = open(self.devfile, 'wb',0)
if self.portId == 0:
Bc.printError("Could not open " + devfile + " for write")
return False
else:
#Bc.printInfo("Succesfully opened write port to " + self.devfile)
if self.dummy:
self.dummyId = open("./writeLog_" + str(WritePort.writePortCount), 'w')
Bc.printInfo("Opened dummy port with id " + str(self.dummyId))
return True
def __init__(self, devfile, width, dummy=False):
if width%8 != 0:
Bc.printError("width: " + str(width) + " is no multiple of 8 bits (1 byte)")
else:
self.devfile = devfile
self.width = width
self.portId = 0
self.totalBytesForTransmission = 0
self.totalBytesTransmitted = 0
WritePort.writePortCount += 1
self.dummy = dummy
self.dummyId = 0
def turn_on(self, channel=1):
Bcolors.printInfo("Rigol DP832A - Turning ON channel " + str(channel))
self.rigol.outputOn(channel)
def read_addr(addr, writePort):
instruction = (instructions.spi_write << 29) | addr
Bcolors.printInfo("Reading addr " + str(addr))
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(addr))
writePort.sendInt(instruction)
def run_input_vector(name, vddc, clockfreq):
vectorfn = name
# vectorfn = 'input_vector_C1'
configfn = "../input_vectors/" + vectorfn + ".config"
# print("OSCAR MEASUREMENT SETUP")
# print("Thomas Vandenabeele\n")
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32", 32)
readPort = ReadPort("/dev/xillybus_read_32", 32)
print(">> Connecting to FIFOs...")
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
# Reading settings
with open(configfn, 'r') as cfgfile:
cfg = yaml.load(cfgfile, yaml.Loader)
print(">> Configuring power supply...")
rigol = RigolDP832A("10.11.98.59")
rigol.set_voltage(cfg['vdd'], 1)
rigol.set_voltage(cfg['vdde'], 2)
rigol.set_voltage(vddc, 3)
rigol.turn_on_all()
time.sleep(0.5)
print(">> Configuring clock frequency...")
# Set clock frequency
real_freq = chip.set_clock(clockfreq, writePort)
#print("Real freq: " + str(real_freq))
Bcolors.printPassed("CLOCK - Real frequency is " + str(real_freq) + "MHz")
time.sleep(1)
print(">> Sending reset pulse...")
# Reset chip
chip.reset(readPort, writePort)
time.sleep(0.5)
# Send a program to the chip
print(">> Sending data to memory...")
chip.enable_write_mode(writePort)
vector = '../input_vectors/' + vectorfn + '.in'
with open(vector) as fp:
line = fp.readline()
while line:
#print("Vector instruction: {}".format(line.strip()))
instr = re.split(' |; |, |\*|\t', line)
addr = (int(instr[0][0:4], 16))
value = (int(instr[1][0:4], 16))
chip.write_to_mem(addr, value, writePort)
line = fp.readline()
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
#input("Change clock and press Enter to continue...")
time.sleep(0.5)
print(">> Sending start pulse...")
chip.start(writePort)
time.sleep(5)
result_array = []
for ntimes in range(cfg['n_readout']):
print(">> Reading back results...")
now = datetime.now()
date_time = now.strftime("%m%d-%H%M%S")
filename = "../results/" + str(date_time) + "_spi-results.txt"
chip.readout_memory(readPort, writePort, 0, 7, filename,
const.WR_MEMORY)
print(">> Checking results...")
outputfn = "../output_vectors/" + vectorfn + ".out"
vectorreffn = "../input_vectors/" + vectorfn + ".out"
correct = compare_results.check(configfn, vectorreffn, filename,
outputfn)
os.remove(filename)
result_array.append(correct)
# with open("../input_vectors/" + vectorfn + ".config", 'r') as cfgfile:
# cfg = yaml.load(cfgfile, yaml.Loader)
# ct_size = cfg['plaintext_size']
# tag_size = cfg['tag_size']
#
# out = open("../output_vectors/" + vectorfn + ".out", "w")
# out.write("#C\n")
# with open(filename) as fp:
# line = fp.readline()
# while line:
# byte1 = line[0:2]
# byte2 = line[2:4]
#
# for i in range(2):
# if ct_size > 0:
# out.write(line[i*2 : i*2+2].upper() + "\n")
# ct_size -= 1
# elif ct_size == 0:
# if tag_size == cfg['tag_size']:
# out.write("#T\n")
# line = fp.readline()
# if ct_size == 0:
# for i in range(2):
# if tag_size > 0:
# out.write(line[i*2 : i*2+2].upper() + "\n")
# tag_size -= 1
#
# line = fp.readline()
# out.close()
vddc_real = rigol.get_real_voltage(3)
print(">> Closing connections...")
# Close ports
writePort.closePort()
readPort.closePort()
rigol.stop()
return vddc_real, real_freq, result_array
def write_mem(n_addr, writePort):
Bcolors.printInfo("Writing memory from 0 to {} ...".format(n_addr))
instruction = (instructions.write_prog << 29) | n_addr
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(instruction))
writePort.sendInt(instruction)
def enable_exit_mode(writePort):
Bcolors.printInfo("Enabling EXIT mode ...")
data = (4095 << 4) | 3
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(data))
instruction = (instructions.spi_write << 29) | data
writePort.sendInt(instruction)
def enable_read_mode(memory, writePort):
Bcolors.printInfo("Enabling READ mode for memory " + str(memory) + " ...")
data = (4095 << 4) | (memory << 2) | 0
#Bcolors.printInfo("Instruction: " + "0x{:04x}".format(data))
instruction = (instructions.spi_write << 29) | data
writePort.sendInt(instruction)
def start(writePort):
Bcolors.printInfo("Sending start pulse ...")
instruction = (instructions.chip_start << 29)
writePort.sendInt(instruction)
def findNearestFrequency(self, frequency, verbose=False):
idx = (abs(self.frequencies-frequency)).argmin()
if verbose:
Bcolors.printInfo("Nearest frequency = " + str(self.frequencies[idx]) + " for requested frequency " + str(frequency))
return self.frequencies[idx]
def run_input_vector(name):
vectorfn = name
# vectorfn = 'input_vector_C1'
configfn = "../input_vectors/" + vectorfn + ".config"
# print("OSCAR MEASUREMENT SETUP")
# print("Thomas Vandenabeele\n")
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32",32)
readPort = ReadPort("/dev/xillybus_read_32",32)
print(">> Connecting to FIFOs...")
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
# Reading settings
with open(configfn, 'r') as cfgfile:
cfg = yaml.load(cfgfile, yaml.Loader)
print(">> Configuring power supply...")
rigol = RigolDP832A("10.11.98.59")
rigol.set_voltage(cfg['vdd'], 1)
rigol.set_voltage(cfg['vdde'], 2)
rigol.set_voltage(cfg['vddc'], 3)
rigol.turn_on_all()
time.sleep(0.5)
print(">> Configuring clock frequency...")
# Set clock frequency
real_freq = chip.set_clock(cfg['clock'], writePort)
#print("Real freq: " + str(real_freq))
Bcolors.printPassed("CLOCK - Real frequency is " + str(real_freq) + "MHz")
time.sleep(1)
print(">> Sending reset pulse...")
# Reset chip
chip.reset(readPort, writePort)
time.sleep(0.5)
# Send a program to the chip
print(">> Sending data to memory...")
chip.enable_write_mode(writePort)
vector = '../input_vectors/' + vectorfn + '.in'
with open(vector) as fp:
line = fp.readline()
while line:
#print("Vector instruction: {}".format(line.strip()))
instr = re.split(' |; |, |\*|\t',line)
addr = (int(instr[0][0:4], 16))
value = (int(instr[1][0:4], 16))
chip.write_to_mem(addr, value, writePort)
line = fp.readline()
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
#input("Change clock and press Enter to continue...")
time.sleep(0.5)
print(">> Sending start pulse...")
chip.start(writePort)
time.sleep(5)
out = open("outputtest.txt", "w")
for i in range(1000):
correct = readout_compare_results(readPort, writePort, vectorfn, configfn)
out.write(str(correct) + "\n")
time.sleep(0.1)
out.close()
print(">> Closing connections...")
# Close ports
writePort.closePort()
readPort.closePort()
rigol.stop()
return correct
def turn_on_all(self):
Bcolors.printInfo("Rigol DP832A - Turning ON all channels")
self.rigol.outputOnAll()
def turn_off_all(self):
Bcolors.printInfo("Rigol DP832A - Turning OFF all channels")
self.rigol.outputOffAll()
def get_real_voltage(self, channel=1):
Bcolors.printInfo("Rigol DP832A - Getting real voltage on channel " +
str(channel))
return self.rigol.measureVoltage(channel)
