def chip_setup():
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32", 32)
readPort = ReadPort("/dev/xillybus_read_32", 32)
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
# Send a program to the chip
chip.reset(readPort, writePort)
#time.sleep(0.5)
chip.enable_exit_mode(writePort)
now = datetime.now()
date_time = now.strftime("%m%d%Y-%H%M%S")
filename = "../results/" + str(date_time) + "_spi-results.txt"
chip.readout_memory(readPort, writePort, 0, 20, const.WR_MEMORY, filename)
# Close ports
writePort.closePort()
readPort.closePort()
return
def chip_setup():
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32",32)
readPort = ReadPort("/dev/xillybus_read_32",32)
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
real_freq = chip.set_clock(100, writePort)
print("Real freq: " + str(real_freq))
time.sleep(2.5)
chip.start(writePort)
# Send a program to the chip
chip.reset(readPort, writePort)
# Close ports
writePort.closePort()
readPort.closePort()
return
def chip_setup():
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32", 32)
readPort = ReadPort("/dev/xillybus_read_32", 32)
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
print(">> Configuring power supply...")
rigol = RigolDP832A("10.11.98.59")
rigol.set_voltage(1, 1)
rigol.set_voltage(1.8, 2)
rigol.set_voltage(0, 3)
rigol.turn_on_all()
time.sleep(0.5)
# Set clock frequency
real_freq = chip.set_clock(10, writePort)
print("Real freq: " + str(real_freq))
time.sleep(1)
# Send reset to the chip
chip.reset(readPort, writePort)
time.sleep(0.5)
chip.enable_write_mode(writePort)
i = 1
while i < 101:
chip.write_to_mem(i, i, writePort)
# input("Press Enter to continue...")
i = i + 1
# input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
# input("Press Enter to continue...")
now = datetime.now()
date_time = now.strftime("%m%d%Y-%H%M%S")
filename = "../results/" + str(date_time) + "_spi-results.txt"
chip.readout_memory(readPort, writePort, 0, 42, filename, const.RD_MEMORY)
# Close ports
writePort.closePort()
readPort.closePort()
rigol.stop()
return
def chip_setup():
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32", 32)
readPort = ReadPort("/dev/xillybus_read_32", 32)
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
chip.start(writePort)
time.sleep(2.5)
# Send a program to the chip
chip.reset(readPort, writePort)
real_freq = chip.set_clock(10, writePort)
print("Real freq: " + str(real_freq))
time.sleep(0.5)
chip.enable_write_mode(writePort)
chip.write_to_mem(1, 170, writePort)
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
#input("Press Enter to continue...")
chip.enable_read_mode(0, writePort)
#input("Press Enter to continue...")
# i=0
# while i<2048:
# chip.read_addr(i, writePort)
# i = i+1
# time.sleep(0.1)
chip.read_addr(1, writePort)
chip.clear_results(readPort)
#input("Press Enter to continue...")
chip.read_addr(1, writePort)
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
time.sleep(0.5)
chip.readout_results(readPort, 100)
# Close ports
writePort.closePort()
readPort.closePort()
return
from lib.ReadPort import ReadPort
import lib.commands_chip as chip
import lib.constants as const
from datetime import datetime
import time
import re
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32",32)
readPort = ReadPort("/dev/xillybus_read_32",32)
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
# Send a program to the chip
chip.reset(readPort, writePort)
#time.sleep(0.5)
print("Sending data to RAM")
# Set the clock frequency
real_freq = chip.set_clock(25, writePort)
print("Real freq: " + str(real_freq))
# Close ports
writePort.closePort()
readPort.closePort()
def run_input_vector(name):
vectorfn = name
# vectorfn = 'input_vector_C1'
configfn = "../input_vectors/" + vectorfn + ".config"
# print("OSCAR MEASUREMENT SETUP")
# print("Thomas Vandenabeele\n")
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32",32)
readPort = ReadPort("/dev/xillybus_read_32",32)
print(">> Connecting to FIFOs...")
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" + Bcolors.ENDC)
# Reading settings
with open(configfn, 'r') as cfgfile:
cfg = yaml.load(cfgfile, yaml.Loader)
print(">> Configuring power supply...")
rigol = RigolDP832A("10.11.98.59")
rigol.set_voltage(cfg['vdd'], 1)
rigol.set_voltage(cfg['vdde'], 2)
rigol.set_voltage(cfg['vddc'], 3)
rigol.turn_on_all()
time.sleep(0.5)
print(">> Configuring clock frequency...")
# Set clock frequency
real_freq = chip.set_clock(cfg['clock'], writePort)
#print("Real freq: " + str(real_freq))
Bcolors.printPassed("CLOCK - Real frequency is " + str(real_freq) + "MHz")
time.sleep(1)
print(">> Sending reset pulse...")
# Reset chip
chip.reset(readPort, writePort)
time.sleep(0.5)
# Send a program to the chip
print(">> Sending data to memory...")
chip.enable_write_mode(writePort)
vector = '../input_vectors/' + vectorfn + '.in'
with open(vector) as fp:
line = fp.readline()
while line:
#print("Vector instruction: {}".format(line.strip()))
instr = re.split(' |; |, |\*|\t',line)
addr = (int(instr[0][0:4], 16))
value = (int(instr[1][0:4], 16))
chip.write_to_mem(addr, value, writePort)
line = fp.readline()
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
#input("Change clock and press Enter to continue...")
time.sleep(0.5)
print(">> Sending start pulse...")
chip.start(writePort)
time.sleep(5)
out = open("outputtest.txt", "w")
for i in range(1000):
correct = readout_compare_results(readPort, writePort, vectorfn, configfn)
out.write(str(correct) + "\n")
time.sleep(0.1)
out.close()
print(">> Closing connections...")
# Close ports
writePort.closePort()
readPort.closePort()
rigol.stop()
return correct
def run_input_vector(name, vddc, clockfreq):
vectorfn = name
# vectorfn = 'input_vector_C1'
configfn = "../input_vectors/" + vectorfn + ".config"
# print("OSCAR MEASUREMENT SETUP")
# print("Thomas Vandenabeele\n")
#Setup read and write port
writePort = WritePort("/dev/xillybus_write_32", 32)
readPort = ReadPort("/dev/xillybus_read_32", 32)
print(">> Connecting to FIFOs...")
if not writePort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
quit()
if not readPort.openPort():
print(Bcolors.FAIL + "Could not open write port, quitting" +
Bcolors.ENDC)
# Reading settings
with open(configfn, 'r') as cfgfile:
cfg = yaml.load(cfgfile, yaml.Loader)
print(">> Configuring power supply...")
rigol = RigolDP832A("10.11.98.59")
rigol.set_voltage(cfg['vdd'], 1)
rigol.set_voltage(cfg['vdde'], 2)
rigol.set_voltage(vddc, 3)
rigol.turn_on_all()
time.sleep(0.5)
print(">> Configuring clock frequency...")
# Set clock frequency
real_freq = chip.set_clock(clockfreq, writePort)
#print("Real freq: " + str(real_freq))
Bcolors.printPassed("CLOCK - Real frequency is " + str(real_freq) + "MHz")
time.sleep(1)
print(">> Sending reset pulse...")
# Reset chip
chip.reset(readPort, writePort)
time.sleep(0.5)
# Send a program to the chip
print(">> Sending data to memory...")
chip.enable_write_mode(writePort)
vector = '../input_vectors/' + vectorfn + '.in'
with open(vector) as fp:
line = fp.readline()
while line:
#print("Vector instruction: {}".format(line.strip()))
instr = re.split(' |; |, |\*|\t', line)
addr = (int(instr[0][0:4], 16))
value = (int(instr[1][0:4], 16))
chip.write_to_mem(addr, value, writePort)
line = fp.readline()
#input("Press Enter to continue...")
chip.enable_exit_mode(writePort)
#input("Change clock and press Enter to continue...")
time.sleep(0.5)
print(">> Sending start pulse...")
chip.start(writePort)
time.sleep(5)
result_array = []
for ntimes in range(cfg['n_readout']):
print(">> Reading back results...")
now = datetime.now()
date_time = now.strftime("%m%d-%H%M%S")
filename = "../results/" + str(date_time) + "_spi-results.txt"
chip.readout_memory(readPort, writePort, 0, 7, filename,
const.WR_MEMORY)
print(">> Checking results...")
outputfn = "../output_vectors/" + vectorfn + ".out"
vectorreffn = "../input_vectors/" + vectorfn + ".out"
correct = compare_results.check(configfn, vectorreffn, filename,
outputfn)
os.remove(filename)
result_array.append(correct)
# with open("../input_vectors/" + vectorfn + ".config", 'r') as cfgfile:
# cfg = yaml.load(cfgfile, yaml.Loader)
# ct_size = cfg['plaintext_size']
# tag_size = cfg['tag_size']
#
# out = open("../output_vectors/" + vectorfn + ".out", "w")
# out.write("#C\n")
# with open(filename) as fp:
# line = fp.readline()
# while line:
# byte1 = line[0:2]
# byte2 = line[2:4]
#
# for i in range(2):
# if ct_size > 0:
# out.write(line[i*2 : i*2+2].upper() + "\n")
# ct_size -= 1
# elif ct_size == 0:
# if tag_size == cfg['tag_size']:
# out.write("#T\n")
# line = fp.readline()
# if ct_size == 0:
# for i in range(2):
# if tag_size > 0:
# out.write(line[i*2 : i*2+2].upper() + "\n")
# tag_size -= 1
#
# line = fp.readline()
# out.close()
vddc_real = rigol.get_real_voltage(3)
print(">> Closing connections...")
# Close ports
writePort.closePort()
readPort.closePort()
rigol.stop()
return vddc_real, real_freq, result_array