def do_finalize(self):
if self.separate_rw:
self.submodules.write_converter = LiteDRAMNativePortConverter(
self.write_user_port, self.write_crossbar_port)
self.submodules.read_converter = LiteDRAMNativePortConverter(
self.read_user_port, self.read_crossbar_port)
else:
self.submodules.converter = LiteDRAMNativePortConverter(
self.write_user_port, self.write_crossbar_port)
def __init__(self, wishbone, port, base_address=0x00000000):
wishbone_data_width = len(wishbone.dat_w)
port_data_width = 2**int(log2(len(
port.wdata.data))) # Round to lowest power 2
if wishbone_data_width != port_data_width:
if wishbone_data_width > port_data_width:
addr_shift = -log2_int(wishbone_data_width // port_data_width)
else:
addr_shift = log2_int(port_data_width // wishbone_data_width)
new_port = LiteDRAMNativePort(mode=port.mode,
address_width=port.address_width +
addr_shift,
data_width=wishbone_data_width)
self.submodules += LiteDRAMNativePortConverter(new_port, port)
port = new_port
# # #
adr_offset = base_address >> log2_int(port.data_width // 8)
# latch ready signals of cmd/wdata and then wait until all are ready
cmd_consumed = Signal()
wdata_consumed = Signal()
self.sync += [
If(
wishbone.ack,
cmd_consumed.eq(0),
wdata_consumed.eq(0),
).Else(
If(port.cmd.valid & port.cmd.ready, cmd_consumed.eq(1)),
If(port.wdata.valid & port.wdata.ready, wdata_consumed.eq(1)),
),
]
ack_cmd = Signal()
ack_wdata = Signal()
ack_rdata = Signal()
self.comb += [
port.cmd.addr.eq(wishbone.adr - adr_offset),
port.cmd.we.eq(wishbone.we),
port.wdata.data.eq(wishbone.dat_w),
port.wdata.we.eq(wishbone.sel),
wishbone.dat_r.eq(port.rdata.data),
# always wait for reads, flush write when transaction ends
port.flush.eq(~wishbone.cyc),
port.cmd.last.eq(~wishbone.we),
# make sure cmd/wdata won't stay valid after it is consumed
port.cmd.valid.eq(wishbone.cyc & wishbone.stb & ~cmd_consumed),
port.wdata.valid.eq((port.cmd.valid | cmd_consumed) & port.cmd.we
& ~wdata_consumed),
port.rdata.ready.eq((port.cmd.valid | cmd_consumed)
& ~port.cmd.we),
wishbone.ack.eq(ack_cmd & (
(wishbone.we & ack_wdata) | (~wishbone.we & ack_rdata))),
ack_cmd.eq((port.cmd.valid & port.cmd.ready) | cmd_consumed),
ack_wdata.eq((port.wdata.valid & port.wdata.ready)
| wdata_consumed),
ack_rdata.eq(port.rdata.valid & port.rdata.ready),
]
def __init__(self, user_data_width, native_data_width):
# write port and converter
self.write_user_port = LiteDRAMNativeWritePort(
address_width=32, data_width=user_data_width)
self.write_crossbar_port = LiteDRAMNativeWritePort(
address_width=32, data_width=native_data_width)
write_converter = LiteDRAMNativePortConverter(self.write_user_port,
self.write_crossbar_port)
self.submodules += write_converter
# read port and converter
self.read_user_port = LiteDRAMNativeReadPort(
address_width=32, data_width=user_data_width)
self.read_crossbar_port = LiteDRAMNativeReadPort(
address_width=32, data_width=native_data_width)
read_converter = LiteDRAMNativePortConverter(self.read_user_port,
self.read_crossbar_port)
self.submodules += read_converter
# memory
self.memory = DRAMMemory(native_data_width, 128)
def get_port(self,
mode="both",
data_width=None,
clock_domain="sys",
reverse=False,
**kwargs):
# retro-compatibility # FIXME: remove
if "cd" in kwargs:
print(
"[WARNING] Please update LiteDRAMCrossbar.get_port's \"cd\" parameter to \"clock_domain\""
)
clock_domain = kwargs["cd"]
if "dw" in kwargs:
print(
"[WARNING] Please update LiteDRAMCrossbar.get_port's \"dw\" parameter to \"data_width\""
)
data_width = kwargs["dw"]
if self.finalized:
raise FinalizeError
if data_width is None:
# use internal data_width when no width adaptation is requested
data_width = self.controller.data_width
# crossbar port
port = LiteDRAMNativePort(
mode=mode,
address_width=self.rca_bits + self.bank_bits - self.rank_bits,
data_width=self.controller.data_width,
clock_domain="sys",
id=len(self.masters),
with_bank=self.controller.settings.with_reordering)
self.masters.append(port)
# clock domain crossing
if clock_domain != "sys":
new_port = LiteDRAMNativePort(
mode=mode,
address_width=port.address_width,
data_width=port.data_width,
clock_domain=clock_domain,
id=port.id,
with_bank=self.controller.settings.with_reordering)
self.submodules += LiteDRAMNativePortCDC(new_port, port)
port = new_port
# data width convertion
if data_width != self.controller.data_width:
if data_width > self.controller.data_width:
addr_shift = -log2_int(
data_width // self.controller.data_width)
else:
addr_shift = log2_int(self.controller.data_width // data_width)
new_port = LiteDRAMNativePort(
mode=mode,
address_width=port.address_width + addr_shift,
data_width=data_width,
clock_domain=clock_domain,
id=port.id,
with_bank=self.controller.settings.with_reordering)
self.submodules += ClockDomainsRenamer(clock_domain)(
LiteDRAMNativePortConverter(new_port, port, reverse))
port = new_port
return port