def __init__(self, platform, csr_data_width=8, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
csr_data_width=csr_data_width,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
bios_size = 0x8000
# sdram
sdram_module = K4B2G1646F(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
l2_size=32,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="Arty DMA Test SoC",
ident_version=True,
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.oled = oled.OLED(platform.request("oled"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# sdram bist
generator_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.generator = LiteDRAMBISTGenerator(generator_port)
checker_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.checker = LiteDRAMBISTChecker(checker_port)
def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type=None,
l2_size=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# uart
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq))
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.oled = oled.OLED(platform.request("oled"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region(
"spiflash", self.mem_map["spiflash"], 16*1024*1024)
self.add_interrupt("uart")
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
# sdram
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self, **kwargs):
platform = nexys4ddr.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT47H64M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(
self,
platform,
clk_freq,
integrated_rom_size=0x5000,
integrated_sram_size=0x4000,
#shadow_base=0x00000000,
ident="NeTV2 LiteX Base SoC",
reserve_nmi_interrupt=False,
cpu_type="vexriscv",
cpu_variant="debug",
**kwargs)
self.comb += self.uart.reset.eq(self.cpu_or_bridge.debug_reset)
self.submodules.crg = CRG(platform)
# self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("fpga_led0", 0).eq(
self.sys_led ^ self.pcie_led) #TX0 green
self.comb += platform.request("fpga_led1", 0).eq(0) #TX0 red
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, **kwargs):
kwargs['cpu_type'] = None
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
with_uart=False,
**kwargs)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
self.clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# sdram bist
ddr_generator_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.ddr_generator = LiteDRAMBISTGenerator(
ddr_generator_port)
ddr_checker_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.ddr_checker = LiteDRAMBISTChecker(ddr_checker_port)
# led blink
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# sdram
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(
platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
controller_settings = ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led)
#checker_port = self.sdram.crossbar.get_port(mode="read")
#self.submodules.checker = LiteDRAMBISTChecker(checker_port)
# led blink
#counter = Signal(32)
#self.sync.clk125 += counter.eq(counter + 1)
#self.comb += platform.request("user_led", 0).eq(counter[26])
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, **kwargs):
platform = nexys_video.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
platform,
**kwargs):
clk_freq = 100*1000000
DbgSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
def __init__(self, platform, csr_data_width=8, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
csr_data_width=csr_data_width,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
# sdram
sdram_module = K4B2G1646F(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x6000,
integrated_sram_size=0x4000,
#shadow_base=0x00000000,
ident="NeTV2 LiteX Reversing SoC",
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=False))
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led)
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
with_uart=False,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.suart.add_uart_pads(platform.request('serial'))
self.submodules.uart = self.suart.uart
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
16 * 1024 * 1024)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_interrupt("uart")
def __init__(self, platform, with_analyzer=False, with_loopback=False):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32, csr_address_width=15, # required for flash spi
integrated_rom_size=0,
integrated_sram_size=0x8000,
with_uart=False,
ident="USB2Sniffer design",
with_timer=False
)
self.submodules.crg = _CRG(platform)
# flash spi
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(clk_freq/25e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram fifo
depth = 32 * 1024 * 1024
self.submodules.dramfifo = ResetInserter()(LiteDRAMFIFO([("data", 32)], depth, 0,
self.sdram.crossbar, preserve_first_last=False))
self.submodules.hugefifo = ResetInserter()(stream.SyncFIFO([("data", 32)], 512))
# debug wishbone
self.add_cpu(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3e6))
self.add_wb_master(self.cpu.wishbone)
# usb phy
usb_pads = platform.request("usb_fifo")
self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024)
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
else:
# usb core
self.submodules.usb_core = USBCore(self.usb_phy, clk_freq)
# usb <--> wishbone
self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# ulpi switch
ulpi_sw = platform.request("ulpi_sw")
self.submodules.ulpi_sw_oe_n = GPIOOut(ulpi_sw.oe_n)
self.submodules.ulpi_sw_s = GPIOOut(ulpi_sw.s)
# ulpi 0
self.submodules.ulpi_phy0 = ULPIPHY(platform.request("ulpi", 0), cd="ulpi0")
self.submodules.ulpi_core0 = ULPICore(self.ulpi_phy0)
# packer0
self.submodules.overflow0 = OverflowMeter(ulpi_cmd_description(8, 1))
self.submodules.iticore0 = ITICore()
self.submodules.fifo0 = ResetInserter()(stream.SyncFIFO([("data", 40), ("len", 2)], 16))
self.submodules.conv40320 = Conv4032()
# ulpi 1
self.submodules.ulpi_phy1 = ULPIPHY(platform.request("ulpi", 1), cd="ulpi1")
self.submodules.ulpi_core1 = ULPICore(self.ulpi_phy1)
# usb <--> ulpi0
self.submodules.wrapcore0 = WrapCore(self.usb_core, self.usb_map["ulpi0"])
self.comb += [
self.ulpi_core0.source.connect(self.overflow0.sink),
self.overflow0.source.connect(self.iticore0.sink),
self.iticore0.source.connect(self.fifo0.sink),
self.fifo0.source.connect(self.conv40320.sink),
self.conv40320.source.connect(self.hugefifo.sink),
self.hugefifo.source.connect(self.dramfifo.sink),
self.dramfifo.source.connect(self.wrapcore0.sink),
]
# reset manager
self.rst_manager = ResetManager([self.iticore0, self.fifo0,
self.conv40320, self.hugefifo,
self.dramfifo, self.wrapcore0])
# leds
led0 = platform.request("rgb_led", 0)
self.submodules.blinker0 = BlinkerRGB(led0,
self.etherbone.packet.tx.source.valid,
0, self.etherbone.packet.rx.sink.valid)
led1 = platform.request("rgb_led", 1)
self.submodules.blinker1 = BlinkerRGB(led1,
self.ulpi_core0.source.valid,
0, self.wrapcore0.sender.source.valid)
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.crg.cd_usb.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0)
if with_analyzer:
analyzer_signals = [
self.ulpi_core0.source.valid,
self.ulpi_core0.source.ready,
self.ulpi_core0.source.data,
self.iticore0.source.valid,
self.iticore0.source.ready,
self.iticore0.source.data,
self.fifo.source.valid,
self.fifo.source.ready,
self.fifo.source.data,
self.wrapcore0.sender.source.valid,
self.wrapcore0.sender.source.ready,
self.wrapcore0.sender.source.data,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, clock_domain="sys")
def __init__(self,
platform,
with_sdram_bist=True, bist_async=True, bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
# uart mux
uart_sel = platform.request("user_sw", 0)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
uart_phys = {
"cpu": UARTVirtualPhy(),
"bridge": UARTVirtualPhy()
}
self.comb += [
If(uart_sel,
self.uart_phy.source.connect(uart_phys["bridge"].source),
uart_phys["bridge"].sink.connect(self.uart_phy.sink),
uart_phys["cpu"].source.ready.eq(1) # avoid stalling cpu
).Else(
self.uart_phy.source.connect(uart_phys["cpu"].source),
uart_phys["cpu"].sink.connect(self.uart_phy.sink),
uart_phys["bridge"].source.ready.eq(1) # avoid stalling bridge
)
]
# uart cpu
self.submodules.uart = UART(uart_phys["cpu"])
# uart bridge
self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
def __init__(self, platform,
with_sdram_bist=True, bist_async=True, bist_random=False):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# uart
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# logic analyzer
analyzer_signals = [Signal(2)]
if False:
analyzer_signals = [
generator_user_port.cmd.valid,
generator_user_port.cmd.ready,
generator_user_port.cmd.we,
generator_user_port.cmd.adr,
generator_user_port.wdata.valid,
generator_user_port.wdata.ready,
generator_user_port.wdata.we,
self.generator.start.re,
self.checker.start.re
]
if False:
gen_data = Signal(32)
read_data = Signal(32)
self.comb += [
gen_data.eq(self.checker.core.gen.o),
read_data.eq(checker_user_port.rdata.data)
]
analyzer_signals = [
checker_user_port.cmd.valid,
checker_user_port.cmd.ready,
checker_user_port.cmd.we,
checker_user_port.cmd.adr,
checker_user_port.rdata.valid,
checker_user_port.rdata.ready,
self.generator.start.re,
self.checker.start.re,
gen_data,
read_data,
self.checker.core.errors
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
# self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
16 * 1024 * 1024)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# sdram
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self,
platform,
with_cpu=False,
with_analyzer=True,
with_loopback=False):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type="lm32" if with_cpu else None,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_sram_size=0x8000,
with_uart=with_cpu,
ident="PCIe Injector example design",
with_timer=with_cpu)
self.submodules.crg = _CRG(platform)
if not with_cpu:
# use serial as wishbone bridge when no cpu
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=3000000))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# pcie endpoint
self.submodules.pciephy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
cd="sys")
# usb core
usb_pads = platform.request("usb_fifo")
# self.submodules.usb_phy = FT245PHYSynchronous(usb_pads, clk_freq, fifo_depth=16)
self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024)
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(
phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
else:
self.submodules.usb_core = USBCore(self.usb_phy, clk_freq)
# usb <--> wishbone
self.submodules.etherbone = Etherbone(self.usb_core,
self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# usb <--> tlp
self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"])
self.comb += [
self.pciephy.source.connect(self.tlp.sender.sink),
self.tlp.receiver.source.connect(self.pciephy.sink)
]
# wishbone --> msi
self.submodules.msi = MSI()
self.comb += self.msi.source.connect(self.pciephy.msi)
# led blink
usb_counter = Signal(32)
self.sync.usb += usb_counter.eq(usb_counter + 1)
self.comb += platform.request("user_led", 0).eq(usb_counter[26])
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.crg.cd_usb.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0)
self.platform.add_period_constraint(
self.platform.lookup_request("pcie_x1").clk_p, 10.0)
if with_analyzer:
analyzer_signals = [
self.pciephy.sink.valid, self.pciephy.sink.ready,
self.pciephy.sink.last, self.pciephy.sink.dat,
self.pciephy.sink.be, self.pciephy.source.valid,
self.pciephy.source.ready, self.pciephy.source.last,
self.pciephy.source.dat, self.pciephy.source.be
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
1024,
cd="sys")
def __init__(self,
platform,
with_sdram_bist=True,
bist_async=True,
bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(
uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"),
self.clk_freq, 115200)
self.submodules.uart_multiplexer = UARTMultiplexer(
uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(
platform.request("user_sw", 0))
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(
self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(
mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(
mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port,
random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])