Ejemplo n.º 1
0
    def __init__(self,
                 sys_clk_freq=int(125e6),
                 integrated_rom_size=0x8000,
                 **kwargs):
        platform = kcu105.Platform()
        SoCSDRAM.__init__(self,
                          platform,
                          clk_freq=sys_clk_freq,
                          integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)

        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # sdram
        self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                                                   memtype="DDR4",
                                                   sys_clk_freq=sys_clk_freq)
        self.add_csr("ddrphy")
        self.add_constant("USDDRPHY", None)
        sdram_module = EDY4016A(sys_clk_freq, "1:4")
        self.register_sdram(self.ddrphy,
                            sdram_module.geom_settings,
                            sdram_module.timing_settings,
                            main_ram_size_limit=0x40000000)
Ejemplo n.º 2
0
    def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
        platform = kcu105.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
            ident               = "LiteDRAM bench on KCU105",
            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,
            uart_name           = uart)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)
        self.add_csr("crg")

        # DDR4 SDRAM -------------------------------------------------------------------------------
        self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
            memtype          = "DDR4",
            sys_clk_freq     = sys_clk_freq,
            iodelay_clk_freq = 200e6)
        self.add_csr("ddrphy")
        self.add_sdram("sdram",
            phy       = self.ddrphy,
            module    = EDY4016A(sys_clk_freq, "1:4"),
            origin    = self.mem_map["main_ram"],
            size      = 0x40000000,
            with_bist = with_bist,
        )

        # UARTBone ---------------------------------------------------------------------------------
        if uart != "serial":
            self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")

        # Etherbone --------------------------------------------------------------------------------
        self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
            data_pads    = self.platform.request("sfp", 0),
            sys_clk_freq = self.clk_freq)
        self.add_csr("ethphy")
        self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
        self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
        self.add_etherbone(phy=self.ethphy)

        # Analyzer ---------------------------------------------------------------------------------
        if with_analyzer:
            from litescope import LiteScopeAnalyzer
            analyzer_signals = [self.ddrphy.dfi]
            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
                depth        = 256,
                clock_domain = "sys",
                csr_csv      = "analyzer.csv")
            self.add_csr("analyzer")

        # Leds -------------------------------------------------------------------------------------
        from litex.soc.cores.led import LedChaser
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")
Ejemplo n.º 3
0
    def __init__(self,
                 sys_clk_freq=int(200e6),
                 with_pcie=False,
                 pcie_lanes=4,
                 **kwargs):
        platform = quad_hdmi_recorder.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        kwargs["uart_name"] = "crossover"
        SoCCore.__init__(
            self,
            platform,
            sys_clk_freq,
            ident="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # JTAGBone  --------------------------------------------------------------------------------
        self.add_jtagbone()

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(
                pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
                memtype="DDR3",
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=200e6)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT41J256M16(sys_clk_freq, "1:4"),
                           l2_cache_size=kwargs.get("l2_size", 8192))

        # PCIe -------------------------------------------------------------------------------------
        # FIXME: Does not seem to be working when also enabling DRAM. Has been tested succesfully by
        # disabling DRAM with --integrated-main-ram-size=0x100.
        if with_pcie:
            data_width = {
                4: 128,
                8: 256,
            }[pcie_lanes]
            self.submodules.pcie_phy = USPCIEPHY(
                platform,
                platform.request(f"pcie_x{pcie_lanes}"),
                speed="gen3",
                data_width=data_width,
                bar0_size=0x20000)
            self.add_pcie(phy=self.pcie_phy, ndmas=1)
            # False Paths (FIXME: Improve integration).
            platform.toolchain.pre_placement_commands.append(
                "set_false_path -from [get_clocks sys_clk] -to [get_clocks pcie_clk_1]"
            )
            platform.toolchain.pre_placement_commands.append(
                "set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks sys_clk]"
            )
Ejemplo n.º 4
0
    def __init__(self,
                 sys_clk_freq=int(125e6),
                 with_ethernet=False,
                 with_etherbone=False,
                 **kwargs):
        platform = kcu105.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on KCU105",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(
                platform.request("ddram"),
                memtype="DDR4",
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=200e6,
                cmd_latency=1)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=EDY4016A(sys_clk_freq, "1:4"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Ethernet / Etherbone ---------------------------------------------------------------------
        if with_ethernet or with_etherbone:
            self.submodules.ethphy = KU_1000BASEX(
                self.crg.cd_eth.clk,
                data_pads=self.platform.request("sfp", 0),
                sys_clk_freq=self.clk_freq)
            self.add_csr("ethphy")
            self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
            self.platform.add_platform_command(
                "set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
            if with_ethernet:
                self.add_ethernet(phy=self.ethphy)
            if with_etherbone:
                self.add_etherbone(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Ejemplo n.º 5
0
    def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
        platform = kcu105.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         integrated_rom_size=0x8000,
                         integrated_rom_mode="rw",
                         csr_data_width=32,
                         uart_name=uart)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)
        self.add_csr("crg")

        # DDR4 SDRAM -------------------------------------------------------------------------------
        self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                                                   memtype="DDR4",
                                                   sys_clk_freq=sys_clk_freq,
                                                   iodelay_clk_freq=200e6)
        self.add_csr("ddrphy")
        self.add_sdram(
            "sdram",
            phy=self.ddrphy,
            module=EDY4016A(sys_clk_freq, "1:4"),
            origin=self.mem_map["main_ram"],
            size=0x40000000,
        )

        # UARTBone ---------------------------------------------------------------------------------
        if uart != "serial":
            self.add_uartbone(name="serial",
                              clk_freq=100e6,
                              baudrate=115200,
                              cd="uart")

        # Etherbone --------------------------------------------------------------------------------
        self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
                                              data_pads=self.platform.request(
                                                  "sfp", 0),
                                              sys_clk_freq=self.clk_freq)
        self.add_csr("ethphy")
        self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
        self.platform.add_platform_command(
            "set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
        self.add_etherbone(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Ejemplo n.º 6
0
    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
        platform = kcu105.Platform()

        # SoCSDRAM ---------------------------------------------------------------------------------
        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                memtype      = "DDR4",
                sys_clk_freq = sys_clk_freq)
            self.add_csr("ddrphy")
            self.add_constant("USDDRPHY", None)
            sdram_module = EDY4016A(sys_clk_freq, "1:4")
            self.register_sdram(self.ddrphy,
                geom_settings       = sdram_module.geom_settings,
                timing_settings     = sdram_module.timing_settings)
Ejemplo n.º 7
0
    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
        platform = zcu104.Platform()

        # SoCSDRAM ---------------------------------------------------------------------------------
        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(
                platform.request("ddram_32"),  # FIXME: use ddram_64
                memtype="DDR4",
                sim_device="ULTRASCALE_PLUS",
                iodelay_clk_freq=500e6,
                cmd_latency=1,
                sys_clk_freq=sys_clk_freq)
            self.add_csr("ddrphy")
            self.add_constant("USDDRPHY", None)
            sdram_module = KVR21SE15S84(sys_clk_freq, "1:4")
            self.register_sdram(self.ddrphy,
                                geom_settings=sdram_module.geom_settings,
                                timing_settings=sdram_module.timing_settings)
Ejemplo n.º 8
0
    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_pcie=False, with_sata=False, **kwargs):
        platform = kcu105.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on KCU105",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                memtype          = "DDR4",
                sys_clk_freq     = sys_clk_freq,
                iodelay_clk_freq = 200e6)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = EDY4016A(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # Ethernet / Etherbone ---------------------------------------------------------------------
        if with_ethernet or with_etherbone:
            self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
                data_pads    = self.platform.request("sfp", 0),
                sys_clk_freq = self.clk_freq)
            self.add_csr("ethphy")
            self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
            self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
            if with_ethernet:
                self.add_ethernet(phy=self.ethphy)
            if with_etherbone:
                self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)

        # PCIe -------------------------------------------------------------------------------------
        if with_pcie:
            self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
                data_width = 128,
                bar0_size  = 0x20000)
            self.add_csr("pcie_phy")
            self.add_pcie(phy=self.pcie_phy, ndmas=1)

        # SATA -------------------------------------------------------------------------------------
        if with_sata:
            from litex.build.generic_platform import Subsignal, Pins
            from litesata.phy import LiteSATAPHY

            # IOs
            _sata_io = [
                # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
                ("sfp2sata", 0,
                    Subsignal("tx_p", Pins("U4")),
                    Subsignal("tx_n", Pins("U3")),
                    Subsignal("rx_p", Pins("T2")),
                    Subsignal("rx_n", Pins("T1")),
                ),
            ]
            platform.add_extension(_sata_io)

            # RefClk, Generate 150MHz from PLL.
            self.clock_domains.cd_sata_refclk = ClockDomain()
            self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
            sata_refclk = ClockSignal("sata_refclk")
            platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")

            # PHY
            self.submodules.sata_phy = LiteSATAPHY(platform.device,
                refclk     = sata_refclk,
                pads       = platform.request("sfp2sata"),
                gen        = "gen2",
                clk_freq   = sys_clk_freq,
                data_width = 16)
            self.add_csr("sata_phy")

            # Core
            self.add_sata(phy=self.sata_phy, mode="read+write")

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")