def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(50e6)): platform = genesys2.Platform() # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteEth bench on Genesys2", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), with_hw_init_reset=False) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, phy, clk_freq): platform = CorePlatform() SoCCore.__init__(self, platform, clk_freq=clk_freq, cpu_type=None, integrated_rom_size=0x0, integrated_sram_size=0x0, integrated_main_ram_size=0x0, csr_address_width=14, csr_data_width=8, with_uart=False, with_timer=False) self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) # ethernet if phy == "MII": self.submodules.ethphy = LiteEthPHYMII( platform.request("mii_eth_clocks"), platform.request("mii_eth")) elif phy == "RMII": self.submodules.ethphy = LiteEthPHYRMII( platform.request("rmii_eth_clocks"), platform.request("rmii_eth")) elif phy == "GMII": self.submodules.ethphy = LiteEthPHYGMII( platform.request("gmii_eth_clocks"), platform.request("gmii_eth")) elif phy == "RGMII": self.submodules.ethphy = LiteEthPHYRGMII( platform.request("rgmii_eth_clocks"), platform.request("rgmii_eth")) else: ValueError("Unsupported " + phy + " PHY")
def __init__(self, phy="rgmii", **kwargs): assert phy in ["rgmii", "1000basex"] BaseSoC.__init__(self, **kwargs) # RGMII Ethernet PHY ----------------------------------------------------------------------- if phy == "rgmii": self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # 1000BaseX Ethernet PHY ------------------------------------------------------------------- if phy == "1000basex": self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) qpll_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) refclk125 = self.platform.request("gtp_refclk") refclk125_se = Signal() self.specials += \ Instance("IBUFDS_GTE2", i_CEB=0, i_I=refclk125.p, i_IB=refclk125.n, o_O=refclk125_se) qpll = QPLL(refclk125_se, qpll_settings) self.submodules += qpll self.submodules.ethphy = A7_1000BASEX( qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq) self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9 / 62.5e6) self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9 / 62.5e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.txoutclk, self.ethphy.rxoutclk) # Ethernet MAC ----------------------------------------------------------------------------- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # core self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 12.5e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # Etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 20000)) self.add_wb_master(self.cpu_or_bridge.master.bus) self.specials += [ Keep(self.ethphy.crg.cd_eth_rx.clk), Keep(self.ethphy.crg.cd_eth_tx.clk) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get( 'cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if kwargs.get('cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet PHY self.submodules.ethphy = LiteEthPHYRGMII( platform.request("eth_clocks"), platform.request("eth")) self.add_csr("ethphy") # Ethernet MAC ethmac_win_size = 0x2000 self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, ethmac_win_size) self.add_memory_region("ethmac", self.mem_map["ethmac"], ethmac_win_size, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteDRAM bench on Genesys2", ident_version=True, integrated_rom_size=0x10000, integrated_rom_mode="rw", uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], with_bist=with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), with_hw_init_reset=False) self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [self.ddrphy.dfi] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=512, clock_domain="sys", csr_csv="analyzer.csv") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, with_spi_flash=False, **kwargs): platform = mnt_rkx7.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MNT-RKX7", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram( "sdram", phy=self.ddrphy, module=IS43TR16512B(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192), ) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q128JV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), rate="1:1", with_master=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) platform.add_platform_command( "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{main_ethphy_eth_rx_clk_ibuf}}]" ) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # I2C -------------------------------------------------------------------------------------- self.submodules.i2c = I2CMaster(platform.request("i2c"))
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, platform, with_ethernet=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(133e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Daisho USB3.0 Test Design", with_timer=False) self.submodules.crg = _CRG(platform) # uart <--> wishbone self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 7.5) # ethernet PHY and UDP/IP stack if with_ethernet: self.submodules.eth_phy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.eth_core = LiteEthUDPIPCore( self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone( self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, cpu_type=None, mac_address=0x10e2d5000000, ip_address="192.168.100.50", **kwargs): clk_freq = int(142e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, integrated_main_ram_size=0x8000, integrated_rom_size=0x10000, integrated_sram_size=0x8000, csr_data_width=32, with_uart=False, **kwargs) self.submodules.crg = CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) self.add_csr("ethcore") # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(125e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, with_led_chaser=True, **kwargs): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Genesys2", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6)): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size = 0x8000, integrated_rom_mode = "rw", csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"] ) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, *args, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC( phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, phy, clk_freq): platform = CorePlatform() SoCMini.__init__(self, platform, clk_freq=clk_freq) self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) # ethernet if phy == "mii": ethphy = LiteEthPHYMII(platform.request("mii_eth_clocks"), platform.request("mii_eth")) elif phy == "rmii": ethphy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"), platform.request("rmii_eth")) elif phy == "gmii": ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"), platform.request("gmii_eth")) elif phy == "rgmii": ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"), platform.request("rgmii_eth")) else: raise ValueError("Unsupported " + phy + " PHY"); self.submodules.ethphy = ethphy self.add_csr("ethphy")
def __init__(self, with_analyzer=False, host_ip="192.168.1.100", host_udp_port=2000): platform = genesys2.Platform() # BenchSoC --------------------------------------------------------------------------------- BaseSoC.__init__( self, sys_clk_freq=int(100e6), integrated_rom_size=0x10000, integrated_rom_mode="rw", ) # SDCard ---------------------------------------------------------------------------------- self.add_sdcard("sdcard") if with_analyzer: # Etherbone ---------------------------------------------------------------------------- from liteeth.phy.s7rgmii import LiteEthPHYRGMII self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), with_hw_init_reset=False) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [ self.sdblock2mem.sink, self.sdblock2mem.bus, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=2048, clock_domain="sys", csr_csv="analyzer.csv") self.add_csr("analyzer")
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_led_chaser=True, with_sata=False, sata_gen="gen2", vadj="1.2V", with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = nexys_video.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Nexys Video", **kwargs) # CRG -------------------------------------------------------------------------------------- with_video_pll = (with_video_terminal or with_video_framebuffer) self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K256M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html ("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), Subsignal("rx_n", Pins("LPC:DP0_M2C_N")) ), ] platform.add_extension(_sata_io) # PHY self.submodules.sata_phy = LiteSATAPHY(platform.device, pads = platform.request("fmc2sata"), gen = sata_gen, clk_freq = sys_clk_freq, data_width = 16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # VADJ ------------------------------------------------------------------------------------- vadj_map = {"1.2V": 0b00, "1.8V": 0b01, "2.5V": 0b10, "3.3V": 0b11} platform.request_all("vadj").eq(vadj_map[vadj])
def __init__(self, platform, connector="pcie", linerate=2.5e9): assert connector in ["pcie"] sys_clk_freq = int(50e6) # SoCSDRAM ---------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x1000, uart_name="serial", l2_size=0, csr_data_width=32, ) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / 100e6) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Ethernet --------------------------------------------------------------------------------- # phy eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), with_hw_init_reset=False, tx_delay=0e-9, rx_delay=0e-9) self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy) self.add_csr("eth_phy") # core eth_core = LiteEthUDPIPCore(phy=self.eth_phy, mac_address=0x10e2d5000000, ip_address="172.30.28.201", clk_freq=125000000) self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core) # etherbone bridge etherbone_cd = ClockDomain( "etherbone") # similar to sys but need for correct self.clock_domains += etherbone_cd # clock domain renaming self.comb += [ etherbone_cd.clk.eq(ClockSignal("sys")), etherbone_cd.rst.eq(ResetSignal("sys")) ] self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234, cd="etherbone") self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk) # GTP RefClk ------------------------------------------------------------------------------- refclk = Signal() refclk_freq = 100e6 refclk_pads = platform.request("pcie_refclk") self.specials += Instance("IBUFDS_GTE2", i_CEB=0, i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk) # GTP PLL ---------------------------------------------------------------------------------- qpll = GTPQuadPLL(refclk, refclk_freq, linerate) print(qpll) self.submodules += qpll # GTPs ------------------------------------------------------------------------------------- for i in range(2): tx_pads = platform.request(connector + "_tx", i) rx_pads = platform.request(connector + "_rx", i) gtp = GTP(qpll, tx_pads, rx_pads, sys_clk_freq, data_width=20, clock_aligner=False, tx_buffer_enable=True, rx_buffer_enable=True) gtp.add_stream_endpoints() setattr(self.submodules, "gtp" + str(i), gtp) platform.add_period_constraint(gtp.cd_tx.clk, 1e9 / gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9 / gtp.rx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # Record ------------------------------------------------------------------------------------- self.submodules.rx_dma_recorder = LiteDRAMDMAWriter( self.sdram.crossbar.get_port("write", 32, clock_domain="gtp0_rx")) self.rx_dma_recorder.add_csr() self.add_csr("rx_dma_recorder") self.submodules.tx_dma_recorder = LiteDRAMDMAWriter( self.sdram.crossbar.get_port("write", 32, clock_domain="gtp1_rx")) self.tx_dma_recorder.add_csr() self.add_csr("tx_dma_recorder") self.comb += [ self.rx_dma_recorder.sink.valid.eq(self.gtp0.source.valid), self.rx_dma_recorder.sink.data.eq( self.gtp0.source.payload.raw_bits()), self.tx_dma_recorder.sink.valid.eq(self.gtp1.source.valid), self.tx_dma_recorder.sink.data.eq( self.gtp1.source.payload.raw_bits()), ]
def __init__(self, sys_clk_freq=int(125e6), cpu_count=1, with_ethernet=False, **kwargs): VexRiscvSMP.litedram_width = 128 VexRiscvSMP.ibus_width = 64 VexRiscvSMP.dbus_width = 64 VexRiscvSMP.coherent_dma = True platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 kwargs["csr_data_width"] = 8 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant="default", **kwargs) self.add_constant("config_cpu_count", cpu_count) # for dts generation # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [1, 2]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", **kwargs): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # RGMII Ethernet PHY ------------------------------------------------------------------- if ethernet_phy == "rgmii": # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # 1000BaseX Ethernet PHY --------------------------------------------------------------- if ethernet_phy == "1000basex": # phy self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) qpll_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) refclk125 = self.platform.request("gtp_refclk") refclk125_se = Signal() self.specials += \ Instance("IBUFDS_GTE2", i_CEB = 0, i_I = refclk125.p, i_IB = refclk125.n, o_O = refclk125_se) qpll = QPLL(refclk125_se, qpll_settings) self.submodules += qpll self.submodules.ethphy = A7_1000BASEX( qpll_channel=qpll.channels[0], data_pads=self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys Video", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html ("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))), ] platform.add_extension(_sata_io) # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, pads=platform.request("fmc2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii", with_led_chaser=True, with_pcie=False, **kwargs): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AC701", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # RGMII Ethernet PHY ------------------------------------------------------------------- if eth_phy == "rgmii": # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) # 1000BaseX Ethernet PHY --------------------------------------------------------------- if eth_phy == "1000basex": # phy self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) qpll_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) refclk125 = self.platform.request("gtp_refclk") refclk125_se = Signal() self.specials += \ Instance("IBUFDS_GTE2", i_CEB = 0, i_I = refclk125.p, i_IB = refclk125.n, o_O = refclk125_se) qpll = QPLL(refclk125_se, qpll_settings) self.submodules += qpll self.submodules.ethphy = A7_1000BASEX( qpll_channel=qpll.channels[0], data_pads=self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, with_rts_reset=False, with_led_chaser=True, spd_dump=None, **kwargs): platform = berkeleylab_marble.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Berkeley-Lab Marble", **kwargs) # CRG, resettable over USB serial RTS signal ----------------------------------------------- resets = [] if with_rts_reset: ser_pads = platform.lookup_request('serial') resets.append(ser_pads.rts) self.submodules.crg = _CRG(platform, sys_clk_freq, resets) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) if spd_dump is not None: ram_spd = parse_spd_hexdump(spd_dump) ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq) print('DDR3: loaded config from', spd_dump) else: ram_module = MT8JTF12864(sys_clk_freq, "1:4") # KC705 chip, 1 GB print( 'DDR3: No spd data specified, falling back to MT8JTF12864') self.add_sdram( "sdram", phy=self.ddrphy, module=ram_module, # size=0x40000000, # Limit its size to 1 GB l2_cache_size=kwargs.get("l2_size", 8192), with_bist=kwargs.get("with_bist", False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), tx_delay=0) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=True, software_debug=False) if with_etherbone: self.add_etherbone(phy=self.ethphy, buffer_depth=255) # System I2C (behing multiplexer) ---------------------------------------------------------- i2c_pads = platform.request('i2c_fpga') self.submodules.i2c = I2CMaster(i2c_pads) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, connector="pcie", linerate=2.5e9, use_gtp=True): assert connector in ["pcie"] sys_clk_freq = int(50e6) # ********************************************************* # * SoC SDRAM * # ********************************************************* SoCSDRAM.__init__( self, platform, sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x1000, uart_name="serial", l2_size=0, csr_data_width=32, ) # ********************************************************* # * CRG * # ********************************************************* self.submodules.crg = _CRG(platform, sys_clk_freq) platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # ********************************************************* # * DDR3 * # ********************************************************* self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # ********************************************************* # * Ethernet PHY * # ********************************************************* eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), with_hw_init_reset=False, tx_delay=0e-9, rx_delay=0e-9) self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy) self.add_csr("eth_phy") # ********************************************************* # * Ethernet Core * # ********************************************************* eth_core = LiteEthUDPIPCore(phy=self.eth_phy, mac_address=0x10e2d5000000, ip_address="192.168.1.201", clk_freq=125000000) self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core) # ********************************************************* # * Etherbone bridge * # ********************************************************* etherbone_cd = ClockDomain( "etherbone") # similar to sys but need for correct self.clock_domains += etherbone_cd # clock domain renaming self.comb += [ etherbone_cd.clk.eq(ClockSignal("sys")), etherbone_cd.rst.eq(ResetSignal("sys")) ] self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234, cd="etherbone") self.add_wb_master(self.etherbone.wishbone.bus) # ********************************************************* # * Timing constraints for Ethernet * # ********************************************************* self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk) # ********************************************************* # * GTP Refclk * # ********************************************************* if use_gtp: refclk = Signal() refclk_freq = 100e6 refclk_pads = platform.request("pcie_refclk") self.specials += Instance("IBUFDS_GTE2", i_CEB=0, i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk) # ********************************************************* # * GTP PLL * # ********************************************************* qpll = GTPQuadPLL(refclk, refclk_freq, linerate) print(qpll) self.submodules += qpll # ********************************************************* # * GTPs * # ********************************************************* for i in range(2): tx_pads = platform.request(connector + "_tx", i) rx_pads = platform.request(connector + "_rx", i) gtp = GTP(qpll, tx_pads, rx_pads, sys_clk_freq, data_width=20, clock_aligner=False, tx_buffer_enable=True, rx_buffer_enable=True) gtp.add_stream_endpoints() gtp.tx_enable = 0 setattr(self.submodules, "gtp" + str(i), gtp) platform.add_period_constraint(gtp.cd_tx.clk, 1e9 / gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9 / gtp.rx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) else: gtp0_rx_cd = ClockDomain("gtp0_rx") self.clock_domains += gtp0_rx_cd self.comb += [ gtp0_rx_cd.clk.eq(ClockSignal("clk125")), gtp0_rx_cd.rst.eq(ResetSignal("clk125")) ] gtp1_rx_cd = ClockDomain("gtp1_rx") self.clock_domains += gtp1_rx_cd self.comb += [ gtp1_rx_cd.clk.eq(ClockSignal("clk125")), gtp1_rx_cd.rst.eq(ResetSignal("clk125")) ] self.platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp1_rx_cd.clk, gtp0_rx_cd.clk) # ********************************************************* # * Time base * # ********************************************************* time = Signal(32) time_rx = Signal(32) time_tx = Signal(32) self.sync.clk125 += time.eq(time + 1) self.specials += MultiReg(time, time_rx, "gtp0_rx") self.specials += MultiReg(time, time_tx, "gtp1_rx") # ********************************************************* # * RX Capture Pipeline * # ********************************************************* RX_RING_BUFFER_BASE_ADDRESS = 0 RX_RING_BUFFER_SIZE = 0x100000 # Elaborate gtp0_ready gtp0_ready = Signal() if use_gtp: self.specials += MultiReg(qpll.lock & self.gtp0.rx_ready, gtp0_ready, "gtp0_rx") else: gtp0_ready.eq(0) # Request RX DDR3 port rx_port = self.sdram.crossbar.get_port("write", 256) self.submodules.rx_capture = CapturePipeline( "gtp0_rx", rx_port, RX_RING_BUFFER_BASE_ADDRESS, RX_RING_BUFFER_SIZE) self.add_csr("rx_capture") self.add_csr("rx_capture_exerciser_mem") self.add_csr("rx_capture_trigger_mem") if use_gtp: self.comb += self.gtp0.source.connect(self.rx_capture.sink, omit={"valid"}) self.comb += [ self.rx_capture.sink.valid.eq(gtp0_ready | self.rx_capture.simmode), self.rx_capture.time.eq(time_rx), ] # ********************************************************* # * TX Capture Pipeline * # ********************************************************* TX_RING_BUFFER_BASE_ADDRESS = 0x100000 TX_RING_BUFFER_SIZE = 0x100000 # Elaborate gtp1_ready gtp1_ready = Signal() if use_gtp: self.specials += MultiReg(qpll.lock & self.gtp1.rx_ready, gtp1_ready, "gtp1_rx") else: gtp1_ready.eq(0) # Request TX DDR3 port tx_port = self.sdram.crossbar.get_port("write", 256) self.submodules.tx_capture = CapturePipeline( "gtp1_rx", tx_port, TX_RING_BUFFER_BASE_ADDRESS, TX_RING_BUFFER_SIZE) self.add_csr("tx_capture") self.add_csr("tx_capture_exerciser_mem") self.add_csr("tx_capture_trigger_mem") if use_gtp: self.comb += self.gtp1.source.connect(self.tx_capture.sink, omit={"valid"}) self.comb += [ self.tx_capture.sink.valid.eq(gtp1_ready | self.tx_capture.simmode), self.tx_capture.time.eq(time_tx), ] # ********************************************************* # * Recorder RX/TX * # ********************************************************* self.comb += [ self.tx_capture.forced.eq(self.rx_capture.record), self.rx_capture.forced.eq(self.tx_capture.record), self.tx_capture.trigExt.eq(self.rx_capture.trigOut), self.rx_capture.trigExt.eq(self.tx_capture.trigOut), ] # ********************************************************* # * LEDs * # ********************************************************* led_counter = Signal(32) self.sync.gtp0_rx += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[24]) self.comb += platform.request("user_led", 1).eq(0) self.comb += platform.request("user_led", 2).eq(0) self.comb += platform.request("user_led", 3).eq(0)