def __init__(self, platform, connector="pcie", linerate=2.5e9):
assert connector in ["pcie"]
sys_clk_freq = int(100e6)
# SoCMini ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None)
self.submodules.crg = _CRG(platform.request("clk100"), ~platform.request("user_btn", 0))
# GTP RefClk -------------------------------------------------------------------------------
refclk = Signal()
self.comb += refclk.eq(ClockSignal("clk125"))
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# GTP PLL ----------------------------------------------------------------------------------
qpll = GTPQuadPLL(refclk, 125e6, linerate)
print(qpll)
self.submodules += qpll
# GTP --------------------------------------------------------------------------------------
tx_pads = platform.request(connector + "_tx")
rx_pads = platform.request(connector + "_rx")
gtp = GTP(qpll, tx_pads, rx_pads, sys_clk_freq,
data_width = 20,
clock_aligner = False,
tx_buffer_enable = True,
rx_buffer_enable = True)
self.submodules += gtp
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/100e6)
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# Test -------------------------------------------------------------------------------------
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# K28.5 and slow counter --> TX
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:]),
]
# RX (slow counter) --> Leds
for i in range(2):
self.comb += platform.request("user_led", i).eq(gtp.decoders[1].d[i])
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_gtp=True,
gtp_connector="pcie",
gtp_refclk="pcie",
gtp_linerate=5e9,
with_gtp_bist=True,
with_gtp_freqmeter=True,
with_record=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="PCIe Analyzer LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
if with_gtp:
assert gtp_refclk in ["pcie", "internal"]
if gtp_refclk == "pcie":
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
else:
refclk = Signal()
refclk_freq = 100e6
self.comb += refclk.eq(ClockSignal("clk100"))
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]"
)
# GTP PLL ----------------------------------------------------------------------------------
if with_gtp:
qpll = GTPQuadPLL(refclk, refclk_freq, gtp_linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
if with_gtp:
for i in range(2):
tx_pads = platform.request(gtp_connector + "_tx", i)
rx_pads = platform.request(gtp_connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
# GTPs FreqMeters --------------------------------------------------------------------------
if with_gtp_freqmeter:
self.submodules.gtp0_tx_freq = FreqMeter(ClockSignal("gtp0_tx"))
self.submodules.gtp0_rx_freq = FreqMeter(ClockSignal("gtp0_rx"))
self.submodules.gtp1_tx_freq = FreqMeter(ClockSignal("gtp1_tx"))
self.submodules.gtp1_rx_freq = FreqMeter(ClockSignal("gtp1_rx"))
self.add_csr("gtp0_tx_freq")
self.add_csr("gtp0_rx_freq")
self.add_csr("gtp1_tx_freq")
self.add_csr("gtp1_rx_freq")
# GTPs BIST --------------------------------------------------------------------------------
if with_gtp_bist:
self.submodules.gtp0_tx_bist = GTPTXBIST(self.gtp0, "gtp0_tx")
self.submodules.gtp0_rx_bist = GTPRXBIST(self.gtp0, "gtp0_rx")
self.submodules.gtp1_tx_bist = GTPTXBIST(self.gtp1, "gtp1_tx")
self.submodules.gtp1_rx_bist = GTPRXBIST(self.gtp1, "gtp1_rx")
self.add_csr("gtp0_tx_bist")
self.add_csr("gtp0_rx_bist")
self.add_csr("gtp1_tx_bist")
self.add_csr("gtp1_rx_bist")
# Record -----------------------------------------------------------------------------------
# FIXME: use better data/ctrl packing (or separate recorders)
if with_record:
# Convert RX stream from 16-bit@250MHz to 64-bit@sys_clk
rx_converter = stream.StrideConverter([("data", 16), ("ctrl", 2)],
[("data", 96), ("ctrl", 12)],
reverse=False)
rx_converter = ClockDomainsRenamer("gtp0_rx")(rx_converter)
self.submodules.rx_converter = rx_converter
rx_cdc = stream.AsyncFIFO([("data", 96), ("ctrl", 12)],
8,
buffered=True)
rx_cdc = ClockDomainsRenamer({
"write": "gtp0_rx",
"read": "sys"
})(rx_cdc)
self.submodules.rx_cdc = rx_cdc
# RX DMA Recorder
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 128))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.comb += [
gtp.source.connect(rx_converter.sink),
rx_converter.source.connect(rx_cdc.sink),
self.rx_dma_recorder.sink.valid.eq(rx_cdc.source.valid),
self.rx_dma_recorder.sink.data[0:96].eq(rx_cdc.source.data),
self.rx_dma_recorder.sink.data[96:108].eq(rx_cdc.source.ctrl),
]
def __init__(self,
platform,
connector="pcie",
linerate=2.5e9,
use_gtp=True):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# *********************************************************
# * SoC SDRAM *
# *********************************************************
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# *********************************************************
# * CRG *
# *********************************************************
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq)
# *********************************************************
# * DDR3 *
# *********************************************************
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# *********************************************************
# * Ethernet PHY *
# *********************************************************
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# *********************************************************
# * Ethernet Core *
# *********************************************************
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# *********************************************************
# * Etherbone bridge *
# *********************************************************
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# *********************************************************
# * Timing constraints for Ethernet *
# *********************************************************
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# *********************************************************
# * GTP Refclk *
# *********************************************************
if use_gtp:
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# *********************************************************
# * GTP PLL *
# *********************************************************
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# *********************************************************
# * GTPs *
# *********************************************************
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
gtp.tx_enable = 0
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
else:
gtp0_rx_cd = ClockDomain("gtp0_rx")
self.clock_domains += gtp0_rx_cd
self.comb += [
gtp0_rx_cd.clk.eq(ClockSignal("clk125")),
gtp0_rx_cd.rst.eq(ResetSignal("clk125"))
]
gtp1_rx_cd = ClockDomain("gtp1_rx")
self.clock_domains += gtp1_rx_cd
self.comb += [
gtp1_rx_cd.clk.eq(ClockSignal("clk125")),
gtp1_rx_cd.rst.eq(ResetSignal("clk125"))
]
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp1_rx_cd.clk,
gtp0_rx_cd.clk)
# *********************************************************
# * Time base *
# *********************************************************
time = Signal(32)
time_rx = Signal(32)
time_tx = Signal(32)
self.sync.clk125 += time.eq(time + 1)
self.specials += MultiReg(time, time_rx, "gtp0_rx")
self.specials += MultiReg(time, time_tx, "gtp1_rx")
# *********************************************************
# * RX Capture Pipeline *
# *********************************************************
RX_RING_BUFFER_BASE_ADDRESS = 0
RX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp0_ready
gtp0_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp0.rx_ready,
gtp0_ready, "gtp0_rx")
else:
gtp0_ready.eq(0)
# Request RX DDR3 port
rx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.rx_capture = CapturePipeline(
"gtp0_rx", rx_port, RX_RING_BUFFER_BASE_ADDRESS,
RX_RING_BUFFER_SIZE)
self.add_csr("rx_capture")
self.add_csr("rx_capture_exerciser_mem")
self.add_csr("rx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp0.source.connect(self.rx_capture.sink,
omit={"valid"})
self.comb += [
self.rx_capture.sink.valid.eq(gtp0_ready
| self.rx_capture.simmode),
self.rx_capture.time.eq(time_rx),
]
# *********************************************************
# * TX Capture Pipeline *
# *********************************************************
TX_RING_BUFFER_BASE_ADDRESS = 0x100000
TX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp1_ready
gtp1_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp1.rx_ready,
gtp1_ready, "gtp1_rx")
else:
gtp1_ready.eq(0)
# Request TX DDR3 port
tx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.tx_capture = CapturePipeline(
"gtp1_rx", tx_port, TX_RING_BUFFER_BASE_ADDRESS,
TX_RING_BUFFER_SIZE)
self.add_csr("tx_capture")
self.add_csr("tx_capture_exerciser_mem")
self.add_csr("tx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp1.source.connect(self.tx_capture.sink,
omit={"valid"})
self.comb += [
self.tx_capture.sink.valid.eq(gtp1_ready
| self.tx_capture.simmode),
self.tx_capture.time.eq(time_tx),
]
# *********************************************************
# * Recorder RX/TX *
# *********************************************************
self.comb += [
self.tx_capture.forced.eq(self.rx_capture.record),
self.rx_capture.forced.eq(self.tx_capture.record),
self.tx_capture.trigExt.eq(self.rx_capture.trigOut),
self.rx_capture.trigExt.eq(self.tx_capture.trigOut),
]
# *********************************************************
# * LEDs *
# *********************************************************
led_counter = Signal(32)
self.sync.gtp0_rx += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[24])
self.comb += platform.request("user_led", 1).eq(0)
self.comb += platform.request("user_led", 2).eq(0)
self.comb += platform.request("user_led", 3).eq(0)
def __init__(self, platform, connector="pcie", linerate=2.5e9):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# SoCSDRAM ----------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / 100e6)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Ethernet ---------------------------------------------------------------------------------
# phy
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# core
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="172.30.28.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# etherbone bridge
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# GTP PLL ----------------------------------------------------------------------------------
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# Record -------------------------------------------------------------------------------------
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp0_rx"))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.submodules.tx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp1_rx"))
self.tx_dma_recorder.add_csr()
self.add_csr("tx_dma_recorder")
self.comb += [
self.rx_dma_recorder.sink.valid.eq(self.gtp0.source.valid),
self.rx_dma_recorder.sink.data.eq(
self.gtp0.source.payload.raw_bits()),
self.tx_dma_recorder.sink.valid.eq(self.gtp1.source.valid),
self.tx_dma_recorder.sink.data.eq(
self.gtp1.source.payload.raw_bits()),
]
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self, platform, sys_clk, sys_clk_freq, refclk_pads,
refclk_freq, tx_pads, rx_pads):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.enable = Signal(reset=1) # i
self.ready = Signal() # o
self.tx_polarity = Signal() # i
self.tx_idle = Signal() # i
self.tx_pattern = Signal(20) # i
self.rx_polarity = Signal() # i
self.rx_idle = Signal() # o
self.rx_align = Signal() # i
# # #
from liteiclink.transceiver.gtp_7series import GTPQuadPLL, GTP
# Clock ------------------------------------------------------------------------------------
if isinstance(refclk_pads, (Signal, ClockSignal)):
refclk = refclk_pads
else:
refclk = Signal()
self.specials += [
Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
]
# PLL --------------------------------------------------------------------------------------
pll = GTPQuadPLL(refclk, refclk_freq, 5e9)
self.submodules += pll
# Transceiver ------------------------------------------------------------------------------
gtp = gtp = GTP(pll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True,
tx_polarity=self.tx_polarity,
rx_polarity=self.rx_polarity)
gtp.add_stream_endpoints()
tx_datapath = TXDatapath("tx")
rx_substitution = RXErrorSubstitution(gtp, "rx")
rx_datapath = RXDatapath("rx")
self.submodules.gtp = gtp
self.submodules.tx_datapath = tx_datapath
self.submodules.rx_substitution = rx_substitution
self.submodules.rx_datapath = rx_datapath
self.comb += [
gtp.tx_enable.eq(self.enable),
gtp.rx_enable.eq(self.enable),
self.ready.eq(gtp.tx_ready & gtp.rx_ready),
gtp.rx_align.eq(self.rx_align),
self.sink.connect(tx_datapath.sink),
tx_datapath.source.connect(gtp.sink),
gtp.source.connect(rx_substitution.sink),
rx_substitution.source.connect(rx_datapath.sink),
rx_datapath.source.connect(self.source),
]
# Override GTP RX termination for USB3 (800 mV Term Voltage) -------------------------------
gtp.gtp_params.update(p_RX_CM_SEL=0b11,
p_RX_CM_TRIM=0b1010,
p_RXLPM_INCM_CFG=0b1,
p_RXLPM_IPCM_CFG=0b0)
# Override GTP parameters/signals to allow LFPS --------------------------------------------
gtp.gtp_params.update(p_PCS_RSVD_ATTR=0x000000000100,
p_RXOOB_CLK_CFG="FABRIC",
i_SIGVALIDCLK=ClockSignal("oob"),
p_RXOOB_CFG=0b0000110,
i_RXELECIDLEMODE=0b00,
o_RXELECIDLE=self.rx_idle,
i_TXELECIDLE=self.tx_idle)
self.comb += [
gtp.tx_produce_pattern.eq(self.tx_pattern != 0),
gtp.tx_pattern.eq(self.tx_pattern)
]
# Timing constraints -----------------------------------------------------------------------
platform.add_period_constraint(gtp.cd_tx.clk, 1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9 / gtp.rx_clk_freq)
platform.add_false_path_constraints(sys_clk, gtp.cd_tx.clk,
gtp.cd_rx.clk)
def __init__(self, platform, medium="sfp0"):
sys_clk_freq = int(100e6)
SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None)
clk100 = platform.request("clk100")
rst = ~platform.request("user_btn", 0)
self.submodules.crg = _CRG(clk100, rst)
# refclk
refclk = Signal()
self.comb += refclk.eq(ClockSignal("clk125"))
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# pll
qpll = GTPQuadPLL(refclk, 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
if medium == "sfp0":
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
tx_pads = platform.request("sfp_tx", 0)
rx_pads = platform.request("sfp_rx", 0)
elif medium == "sfp1":
self.comb += platform.request("sfp_tx_disable_n", 1).eq(1)
tx_pads = platform.request("sfp_tx", 1)
rx_pads = platform.request("sfp_rx", 1)
else:
raise ValueError
gtp = GTP(qpll, tx_pads, rx_pads, sys_clk_freq, clock_aligner=True)
gtp.add_controls()
self.submodules += gtp
# led blink
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
self.comb += [
gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0)
]
self.crg.cd_sys.clk.attr.add("keep")
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(self.crg.cd_sys.clk, 10)
platform.add_period_constraint(gtp.cd_tx.clk, 1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.cd_tx.clk, gtp.cd_rx.clk)
tx_counter_led = Signal()
tx_counter = Signal(32)
self.sync.tx += tx_counter.eq(tx_counter + 1)
self.comb += tx_counter_led.eq(tx_counter[26])
rx_counter_led = Signal()
rx_counter = Signal(32)
self.sync.rx += rx_counter.eq(rx_counter + 1)
self.comb += rx_counter_led.eq(rx_counter[26])
self.comb += platform.request("user_led", 0).eq(tx_counter_led)
self.comb += platform.request("user_led", 1).eq(rx_counter_led)