def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_sata=False,
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp2sata",
0,
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1")),
Subsignal("rx_p", Pins("G4")),
Subsignal("rx_n", Pins("G3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
from rtl.ticktimer import TickTimer
from rtl.spi import *
import litex.soc.doc as lxsocdoc
# Ish. It's actually slightly smaller, but this is divisible by 4.
GATEWARE_SIZE = 0x1a000
# 1 MB (8 Mb)
SPI_FLASH_SIZE = 1 * 1024 * 1024
io_dvt = [
(
"serial",
0,
Subsignal("rx", Pins("48")), # MON0
Subsignal("tx", Pins("3")), # MON1
IOStandard("LVCMOS33")),
# serial is muxed in with these key monitor pins -- TODO
# ("up5k_keycol0", 0, Pins("48"), IOStandard("LVCMOS33")),
# ("up5k_keycol1", 0, Pins("3"), IOStandard("LVCMOS33")), # this is marking "high"
("up5k_keyrow0", 0, Pins("4"), IOStandard("LVCMOS33")),
("up5k_keyrow1", 0, Pins("2"), IOStandard("LVCMOS33")),
(
"spiflash",
0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS18")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS18")),
Subsignal("cipo", Pins("17"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("14"), IOStandard("LVCMOS18")),
Subsignal("wp", Pins("18"), IOStandard("LVCMOS18")),
def __init__(self,
platform,
boot_source="rand",
debug=None,
bios_file=None,
use_dsp=False,
placer="heap",
output_dir="build",
pnr_seed=0,
warmboot_offsets=None,
**kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self,
platform,
clk_freq,
integrated_sram_size=0,
with_uart=False,
**kwargs)
usb_debug = False
if debug is not None:
if debug == "uart":
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
elif debug == "usb":
usb_debug = True
elif debug == "spi":
import spibone
# Add SPI Wishbone bridge
debug_device = [(
"spidebug",
0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)]
platform.add_extension(debug_device)
spi_pads = platform.request("spidebug")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(
spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# Add a Messible for device->host communications
self.submodules.messible = Messible()
if boot_source == "rand":
kwargs['cpu_reset_address'] = 0
bios_size = 0x2000
self.submodules.random_rom = RandomFirmwareROM(bios_size)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.random_rom.bus, bios_size)
elif boot_source == "bios":
kwargs['cpu_reset_address'] = 0
if bios_file is None:
self.integrated_rom_size = bios_size = 0x2000
self.submodules.rom = wishbone.SRAM(bios_size,
read_only=True,
init=[])
self.register_rom(self.rom.bus, bios_size)
else:
bios_size = 0x2000
self.submodules.firmware_rom = FirmwareROM(
bios_size, bios_file)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.firmware_rom.bus, bios_size)
elif boot_source == "spi":
kwargs['cpu_reset_address'] = 0
self.integrated_rom_size = bios_size = 0x2000
gateware_size = 0x1a000
self.flash_boot_address = self.mem_map["spiflash"] + gateware_size
self.submodules.rom = wishbone.SRAM(bios_size,
read_only=True,
init=[])
self.register_rom(self.rom.bus, bios_size)
else:
raise ValueError(
"unrecognized boot_source: {}".format(boot_source))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(
spi_pads, dummy=platform.spi_dummy, endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=platform.spi_size)
# Add USB pads, as well as the appropriate USB controller. If no CPU is
# present, use the DummyUsb controller.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf,
debug=usb_debug)
else:
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
if usb_debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
# Add GPIO pads for the touch buttons
platform.add_extension(TouchPads.touch_device)
self.submodules.touch = TouchPads(platform.request("touch_pads"))
# Allow the user to reboot the ICE40. Additionally, connect the CPU
# RESET line to a register that can be modified, to allow for
# us to debug programs even during reset.
self.submodules.reboot = SBWarmBoot(self, warmboot_offsets)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.cpu_params.update(
i_externalResetVector=self.reboot.addr.storage, )
self.submodules.rgb = SBLED(platform.revision,
platform.request("rgb_led"))
self.submodules.version = Version(platform.revision,
self,
pnr_seed,
models=[
("0x45", "E", "Fomu EVT"),
("0x44", "D", "Fomu DVT"),
("0x50", "P",
"Fomu PVT (production)"),
("0x48", "H", "Fomu Hacker"),
("0x3f", "?", "Unknown model"),
])
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[
2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.nextpnr_yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.nextpnr_build_template[1] += " --seed " + str(
pnr_seed)
if placer is not None:
platform.toolchain.nextpnr_build_template[
1] += " --placer {}".format(placer)
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
from gateware import ice40
from gateware import cas
from gateware import spi_flash
from targets.utils import define_flash_constants
from platforms import icebreaker
# Alternate serial port, using the second 6-pin PMOD port. Follows Digilent
# PMOD Specification Type 4, so e.g. PMOD USBUART can be used.
pmod_serial = [
("serial", 0,
Subsignal("rx", Pins("PMOD:6")),
Subsignal("tx", Pins("PMOD:5")),
Subsignal("rts", Pins("PMOD:4")),
Subsignal("cts", Pins("PMOD:7")),
IOStandard("LVCMOS33"),
),
]
class _CRG(Module):
def __init__(self, platform):
clk12 = platform.request("clk12")
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
# FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Hans Baier <*****@*****.**>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk.
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
# Leds.
("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")),
# Buttons.
("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")),
("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")),
("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")),
("user_btn", 3, Pins("AD11"), IOStandard("3.3-V LVTTL")),
# Switches
("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")),
# This file is Copyright (c) 2018 William D. Jones <*****@*****.**>
# This file is Copyright (c) 2020 Staf Verhaegen <*****@*****.**>
# License: BSD
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
("rgb_led", 0, Subsignal("r", Pins("J15")), Subsignal("g", Pins("G17")),
Subsignal("b", Pins("F15")), IOStandard("LVCMOS33")),
("rgb_led", 1, Subsignal("r", Pins("E15")), Subsignal("g", Pins("F18")),
Subsignal("b", Pins("E14")), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("M5"), IOStandard("SSTL135")),
("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
("serial", 0, Subsignal("tx", Pins("R12")), Subsignal("rx", Pins("V12")),
IOStandard("LVCMOS33")),
("spi", 0, Subsignal("clk", Pins("G16")), Subsignal("cs_n", Pins("H16")),
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.build.generic_platform import Pins
from litex.build.openfpga import OpenFPGAPlatform
# export LITEX_ENV_OPENFPGA=/home/florent/dev/openfpga/OpenFPGA
# export LITEX_ENV_OPENFPGA_SOFA=/home/florent/dev/openfpga/SOFA
# Minimal Platform ---------------------------------------------------------------------------------
_io = [
("clk", 0, Pins(1)),
("led", 0, Pins(1))
]
class Platform(OpenFPGAPlatform):
def __init__(self):
OpenFPGAPlatform.__init__(self, "FPGA1212_QLSOFA_HD", _io)
# Minimal Design -----------------------------------------------------------------------------------
platform = Platform()
clk = platform.request("clk")
led = platform.request("led")
module = Module()
module.clock_domains.cd_sys = ClockDomain("sys")
module.cd_sys.clk.eq(clk)
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KCU105",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(
platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=EDY4016A(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = KU_1000BASEX(
self.crg.cd_eth.clk,
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = USPCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp2sata",
0,
Subsignal("tx_p", Pins("U4")),
Subsignal("tx_n", Pins("U3")),
Subsignal("rx_p", Pins("T2")),
Subsignal("rx_n", Pins("T1")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
import os.path
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import Pins, Subsignal, IOStandard
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from gateware import info
from gateware import spi_flash
from targets.utils import csr_map_update
serial = [("serial", 0, Subsignal("tx", Pins("GPIO:2")),
Subsignal("rx", Pins("GPIO:1")), IOStandard("LVCMOS33"))]
reset = [
("rst", 0, Pins("GPIO:6"), IOStandard("LVCMOS33")),
]
class _CRG(Module):
def __init__(self, platform):
clk16 = platform.request("clk16")
rst = platform.request("rst")
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
def main():
parser = argparse.ArgumentParser(
description="Build TinyFPGA_BX Main Gateware")
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
)
args = parser.parse_args()
soc = BaseSoC(pnr_seed=args.seed, pnr_placer=args.placer, usb_bridge=True)
channels=2
#ppm_loop_pin = Signal()
pwm_pins = [Signal() for _ in range(channels)]
ppm_input_extension = [("ppm_input_pin", 0, Pins("GPIO:2"), IOStandard("LVCMOS33"))]
soc.platform.add_extension(ppm_input_extension)
ppm_input_pin = soc.platform.request("ppm_input_pin", 0)
soc.submodules.ppm_input = liteppm.PPMinputRegister(ppm_input_pin, servo_pads=pwm_pins, channels=channels)
soc.add_csr("ppm_input")
ppm_output_extension = [("ppm_output_pin", 0, Pins("GPIO:3"), IOStandard("LVCMOS33"))]
soc.platform.add_extension(ppm_output_extension)
ppm_output_pin = soc.platform.request("ppm_output_pin", 0)
soc.submodules.ppm_output = liteppm.PPMoutputRegister(ppm_output_pin, channels=channels)
soc.add_csr("ppm_output")
#pwm_input_extension = [("pwm_input_pin", 0, Pins("GPIO:4"), IOStandard("LVCMOS33"))]
#soc.platform.add_extension(pwm_input_extension)
#pwm_input_pin = soc.platform.request("pwm_input_pin", 0)
soc.submodules.pwm_input = liteppm.PWMinputRegister(ppm_input_pin)
soc.add_csr("pwm_input")
user_led = soc.platform.request("user_led", 0)
soc.submodules.blink = Blink(user_led, ppm_input_pin)
inverter_extension = [
("inverter", 0,
Subsignal("al", Pins("GPIO:4")),
Subsignal("ah", Pins("GPIO:5")),
Subsignal("bl", Pins("GPIO:6")),
Subsignal("bh", Pins("GPIO:7")),
Subsignal("cl", Pins("GPIO:8")),
Subsignal("ch", Pins("GPIO:9")),
IOStandard("LVCMOS33")
)
]
comparator_extension = [
("comparators", 0,
Subsignal("a", Pins("GPIO:10")),
Subsignal("b", Pins("GPIO:11")),
Subsignal("c", Pins("GPIO:12")),
IOStandard("LVCMOS33")
)
]
hall_extension = [
("hall", 0,
Subsignal("a", Pins("GPIO:13")),
Subsignal("b", Pins("GPIO:14")),
Subsignal("c", Pins("GPIO:15")),
IOStandard("LVCMOS33")
)
]
soc.platform.add_extension(inverter_extension)
soc.platform.add_extension(comparator_extension)
soc.platform.add_extension(hall_extension)
inverter_pads = soc.platform.request("inverter")
comp_pads = soc.platform.request("comparators")
hall_pads = soc.platform.request("hall")
inverter_pins = [
[inverter_pads.al, inverter_pads.ah],
[inverter_pads.bl, inverter_pads.bh],
[inverter_pads.cl, inverter_pads.ch]
]
comp_pins = Cat(comp_pads.a, comp_pads.b, comp_pads.c)
hall_pins = Cat(hall_pads.a, hall_pads.b, hall_pads.c)
pt = esc.phase_table(phase_max=12*(2**23))
clk_period = 1e9/16e6
servo_pin = ppm_input_pin
soc.submodules.esc = esc.ESC(pt, clk_period, inverter_pins, comp_pins, hall_pins, servo_pin)
soc.submodules.triv_reg = TrivialRegister()
soc.add_csr("triv_reg")
builder = Builder(soc,
output_dir="build", csr_csv="build/csr.csv",
compile_software=False)
vns = builder.build()
soc.do_exit(vns)
#
# Copyright (c) 2020 David Shah <*****@*****.**>
# Copyright (c) 2020 Florent Kermarrec <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
(
"clk300",
0,
Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
),
(
"clk300",
1,
Subsignal("n", Pins("AW19"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AW20"), IOStandard("DIFF_SSTL12")),
),
(
"clk300",
2,
Subsignal("n", Pins("E32"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("F32"), IOStandard("DIFF_SSTL12")),
),
(
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
if with_video_terminal or with_video_framebuffer:
sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk.
platform = mini_4k.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "jtag_uart"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Blackmagic Decklink Mini 4K",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
("pcie2sata", 0,
Subsignal("tx_p", Pins("B7")),
Subsignal("tx_n", Pins("A7")),
Subsignal("rx_p", Pins("B11")),
Subsignal("rx_n", Pins("A11")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = ClockSignal("sata_refclk"),
pads = platform.request("pcie2sata"),
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoS7GTPHDMIPHY(platform.request("hdmi_out"),
sys_clk_freq = sys_clk_freq,
clock_domain = "hdmi"
)
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # FIXME: Use GTP refclk.
from migen.genlib.io import CRG
from litex.build.generic_platform import Subsignal, IOStandard, Pins
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores import spi_flash
from litex.soc.cores.gpio import GPIOOut
from litex_boards.partner.platforms import tinyfpga_bx
# Peripherals ------------------------------------------------------------------
# Comment out to use default pins (tx=GPIO:0 (A2), rx=GPIO:1 (A1))
tinyfpga_bx.serial = [
("serial", 0, Subsignal("tx", Pins("C2")), Subsignal("rx", Pins("B1")),
IOStandard("LVCMOS33")),
]
# TinyFPGASoC ------------------------------------------------------------------
class TinyLiteX(SoCCore):
"""
Basic SoC for TinyFPGA BX
"""
# Add SPI flash to the Control and Status Register memory space
csr_map = {
"spiflash": 16,
"leds":
# This file is Copyright (c) 2019 Michael Betz <*****@*****.**>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
(
"rgb_led",
0,
Subsignal("r", Pins("N15")),
Subsignal("g", Pins("G17")),
Subsignal("b", Pins("L15")),
IOStandard("LVCMOS33"),
),
(
"rgb_led",
1,
Subsignal("r", Pins("M15")),
Subsignal("g", Pins("L14")),
