def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_usb = ClockDomain()
# # #
# Clk / Rst.
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_hdmi, 40e6)
# USB PLL.
if with_usb_pll:
ulpi = platform.request("ulpi")
self.comb += ulpi.cs.eq(
1) # Enable ULPI chip to enable the ULPI clock.
self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(ulpi.clk, 60e6)
pll.create_clkout(
self.cd_usb, 60e6, phase=-120
) # -120° from DECA's example (also validated with LUNA).
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk50 = platform.request("clk1_50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-7")
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9 / 50e6)
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-7")
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
def __init__(self,
platform,
sys_clk_freq,
with_usb_pll=False,
with_sdram=False,
sdram_rate="1:2",
with_video_terminal=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb = ClockDomain()
if with_video_terminal:
self.clock_domains.cd_hdmi = ClockDomain()
if with_sdram:
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst.
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if with_video_terminal:
pll.create_clkout(self.cd_hdmi, 40e6)
if with_sdram:
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(
self.cd_sys2x_ps, 2 * sys_clk_freq,
phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
if with_sdram:
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
# USB PLL.
if with_usb_pll:
ulpi = platform.request("ulpi")
self.comb += ulpi.cs.eq(
1) # Enable ULPI chip to enable the ULPI clock.
self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(ulpi.clk, 60e6)
pll.create_clkout(
self.cd_usb, 60e6, phase=-120
) # -120° from DECA's example (also validated with LUNA).