def __init__(self, platform, core_config):
platform.add_extension(get_common_ios())
platform.add_extension(get_pcie_ios(core_config["phy_lanes"]))
for i in range(core_config["dma_channels"]):
platform.add_extension(
get_axi_dma_ios(i, core_config["phy_data_width"]))
assert core_config["msi_irqs"] <= 16
platform.add_extension(get_msi_irqs_ios(width=core_config["msi_irqs"]))
sys_clk_freq = int(float(core_config.get("sys_clk_freq")))
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=sys_clk_freq,
csr_data_width=32,
ident="LitePCIe standalone core",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = LitePCIeCRG(platform, sys_clk_freq)
self.add_csr("crg")
# PCIe PHY ---------------------------------------------------------------------------------
self.submodules.pcie_phy = core_config["phy"](
platform,
platform.request("pcie"),
data_width=core_config["phy_data_width"],
bar0_size=core_config["phy_bar0_size"])
self.pcie_phy.use_external_hard_ip("./")
self.add_csr("pcie_phy")
# PCIe Endpoint ----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(
self.pcie_phy, endianness=core_config["endianness"])
# PCIe Wishbone bridge ---------------------------------------------------------------------
pcie_wishbone = LitePCIeWishboneBridge(
self.pcie_endpoint,
lambda a: 1,
qword_aligned=core_config["qword_aligned"])
self.submodules += pcie_wishbone
self.add_wb_master(pcie_wishbone.wishbone)
# PCIe MMAP --------------------------------------------------------------------------------
if core_config["mmap"]:
platform.add_extension(get_axi_lite_mmap_ios(aw=32, dw=32))
wb = wishbone.Interface(data_width=32)
self.add_wb_slave(core_config["mmap_base"], wb,
core_config["mmap_size"])
self.add_memory_region("mmap",
core_config["mmap_base"],
core_config["mmap_size"],
type="io")
axi = AXILiteInterface(data_width=32, address_width=32)
wb2axi = Wishbone2AXILite(wb, axi)
self.submodules += wb2axi
mmap_ios = platform.request("mmap_axi_lite")
self.comb += [
# aw
mmap_ios.awvalid.eq(axi.aw.valid),
axi.aw.ready.eq(mmap_ios.awready),
mmap_ios.awaddr.eq(axi.aw.addr),
# w
mmap_ios.wvalid.eq(axi.w.valid),
axi.w.ready.eq(mmap_ios.wready),
mmap_ios.wstrb.eq(axi.w.strb),
mmap_ios.wdata.eq(axi.w.data),
# b
axi.b.valid.eq(mmap_ios.bvalid),
mmap_ios.bready.eq(axi.b.ready),
axi.b.resp.eq(mmap_ios.bresp),
# ar
mmap_ios.arvalid.eq(axi.ar.valid),
axi.ar.ready.eq(mmap_ios.arready),
mmap_ios.araddr.eq(axi.ar.addr),
# r
axi.r.valid.eq(mmap_ios.rvalid),
mmap_ios.rready.eq(axi.r.ready),
axi.r.data.eq(mmap_ios.rdata),
axi.r.resp.eq(mmap_ios.rresp),
]
# PCIe DMA ---------------------------------------------------------------------------------
pcie_dmas = []
self.add_constant("DMA_CHANNELS", core_config["dma_channels"])
for i in range(core_config["dma_channels"]):
pcie_dma = LitePCIeDMA(
self.pcie_phy,
self.pcie_endpoint,
with_buffering=core_config["dma_buffering"] != 0,
buffering_depth=core_config["dma_buffering"],
with_loopback=core_config["dma_loopback"],
with_synchronizer=core_config["dma_synchronizer"],
with_monitor=core_config["dma_monitor"])
setattr(self.submodules, "pcie_dma" + str(i), pcie_dma)
self.add_csr("pcie_dma{}".format(i))
dma_writer_ios = platform.request("dma{}_writer_axi".format(i))
dma_reader_ios = platform.request("dma{}_reader_axi".format(i))
self.add_interrupt("pcie_dma{}_writer".format(i))
self.add_interrupt("pcie_dma{}_reader".format(i))
self.comb += [
# Writer IOs
pcie_dma.sink.valid.eq(dma_writer_ios.tvalid),
dma_writer_ios.tready.eq(pcie_dma.sink.ready),
pcie_dma.sink.last.eq(dma_writer_ios.tlast),
pcie_dma.sink.data.eq(dma_writer_ios.tdata),
# Reader IOs
dma_reader_ios.tvalid.eq(pcie_dma.source.valid),
pcie_dma.source.ready.eq(dma_reader_ios.tready),
dma_reader_ios.tlast.eq(pcie_dma.source.last),
dma_reader_ios.tdata.eq(pcie_dma.source.data),
]
# PCIe MSI ---------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI(width=32)
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {}
for i in range(core_config["dma_channels"]):
self.interrupts["pcie_dma" + str(i) + "_writer"] = getattr(
self, "pcie_dma" + str(i)).writer.irq
self.interrupts["pcie_dma" + str(i) + "_reader"] = getattr(
self, "pcie_dma" + str(i)).reader.irq
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k.upper() + "_INTERRUPT", i)
assert len(self.interrupts.keys()) <= 16
self.comb += self.pcie_msi.irqs[16:16 + core_config["msi_irqs"]].eq(
platform.request("msi_irqs"))
# 7-Series specific monitoring/flashing features -------------------------------------------
if platform.device[:3] == "xc7":
from litex.soc.cores.dna import DNA
from litex.soc.cores.xadc import XADC
from litex.soc.cores.icap import ICAP
from litex.soc.cores.spi_flash import S7SPIFlash
self.submodules.dna = DNA()
self.add_csr("dna")
self.submodules.xadc = XADC()
self.add_csr("xadc")
self.submodules.icap = ICAP()
self.add_csr("icap")
platform.add_extension(get_flash_ios())
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Acorn CLE 215+",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
self.add_csr("icap")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# PCIe -------------------------------------------------------------------------------------
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
self.comb += platform.request("pcie_clkreq_n").eq(0)
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
# Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
base_address = self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma0")
# DMA1
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_pcie=True,
with_sdram_dmas=False,
with_hdmi_in0=True,
with_hdmi_out0=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
cpu_variant="lite",
l2_size=128,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="NeTV2 LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("icap")
# Flash ------------------------------------------------------------------------------------
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY ----------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=64,
bar0_size=0x20000)
platform.add_false_path_constraint(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint -----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge ----------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 ---------------------------------------------------------------------------------
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1 ---------------------------------------------------------------------------------
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI ----------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# FIXME : Dummy counter capture, connect to HDMI In ------------------------------------
pcie_dma0_counter = Signal(32)
self.sync += [
self.pcie_dma0.sink.valid.eq(1),
If(self.pcie_dma0.sink.ready,
pcie_dma0_counter.eq(pcie_dma0_counter + 1)),
self.pcie_dma0.sink.data.eq(pcie_dma0_counter)
]
pcie_dma1_counter = Signal(32)
self.sync += [
self.pcie_dma1.sink.valid.eq(1),
If(self.pcie_dma1.sink.ready,
pcie_dma1_counter.eq(pcie_dma1_counter + 2)),
self.pcie_dma1.sink.data.eq(pcie_dma1_counter)
]
# SDRAM DMAs -------------------------------------------------------------------------------
if with_sdram_dmas:
self.submodules.sdram_reader = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_reader.add_csr()
self.add_csr("sdram_reader")
self.submodules.sdram_writer = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_writer.add_csr()
self.add_csr("sdram_writer")
# HDMI In 0 --------------------------------------------------------------------------------
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
pads=hdmi_in0_pads,
dram_port=self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6)
# HDMI Out 0 -------------------------------------------------------------------------------
if with_hdmi_out0:
self.submodules.hdmi_out0 = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out", 0),
dram_port=self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=512)
self.add_csr("hdmi_out0")
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)