def __init__(self,
sys_clk_freq=60e6,
with_led_chaser=True,
with_spi_flash=False,
use_internal_osc=False,
sdram_rate="1:1",
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = muselab_icesugar_pro.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Muselab iCESugar Pro",
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_video_pll=with_video_pll,
sdram_rate=sdram_rate)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn,
sys_clk_freq=sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q256
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=W25Q256(Codes.READ_1_1_1))
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"),
clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
with_spi_flash=False, **kwargs):
platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ULX3S",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, with_video_pll, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False
)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import IS25LP128
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_lcd=False,
with_ws2812=False,
**kwargs):
platform = litex_acorn_baseboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on LiteX M2 Baseboard",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_video_pll=with_video_terminal)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"),
clock_domain="hdmi",
pn_swap=["g", "b"])
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
# LCD --------------------------------------------------------------------------------------
if with_lcd:
self.submodules.i2c = I2CMaster(platform.request("lcd"))
# M2 --------------------------------------------------------------------------------------
self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
# WS2812 ----------------------------------------------------------------------------------
if with_ws2812:
from litex.build.generic_platform import Pins, IOStandard
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.led import WS2812
platform.add_extension([("ws2812", 0, Pins("pmod1:0"),
IOStandard("LVCMOS33"))])
self.submodules.ws2812 = WS2812(platform.request("ws2812"),
nleds=64,
sys_clk_freq=sys_clk_freq)
self.bus.add_slave(name="ws2812",
slave=self.ws2812.bus,
region=SoCRegion(
origin=0x2000_0000,
size=64 * 4,
))
def __init__(self,
board="i5",
revision="7.0",
sys_clk_freq=60e6,
with_ethernet=False,
with_etherbone=False,
local_ip="",
remote_ip="",
eth_phy=0,
with_led_chaser=True,
use_internal_osc=False,
sdram_rate="1:1",
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
board = board.lower()
assert board in ["i5", "i9"]
platform = colorlight_i5.Platform(board=board, revision=revision)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Colorlight " + board.upper(),
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=with_usb_pll,
with_video_pll=with_video_pll,
sdram_rate=sdram_rate)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn,
sys_clk_freq=sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if board == "i5":
from litespi.modules import GD25Q16 as SpiFlashModule
if board == "i9":
from litespi.modules import W25Q64 as SpiFlashModule
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L64322A(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
tx_delay=0)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
if local_ip:
local_ip = local_ip.split(".")
self.add_constant("LOCALIP1", int(local_ip[0]))
self.add_constant("LOCALIP2", int(local_ip[1]))
self.add_constant("LOCALIP3", int(local_ip[2]))
self.add_constant("LOCALIP4", int(local_ip[3]))
if remote_ip:
remote_ip = remote_ip.split(".")
self.add_constant("REMOTEIP1", int(remote_ip[0]))
self.add_constant("REMOTEIP2", int(remote_ip[1]))
self.add_constant("REMOTEIP3", int(remote_ip[2]))
self.add_constant("REMOTEIP4", int(remote_ip[3]))
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"),
clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")