def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"):
self.sink = stream.Endpoint(eth_phy_description(dw))
self.source = stream.Endpoint(eth_phy_description(dw))
self.bus = wishbone.Interface()
# # #
# storage in SRAM
sram_depth = eth_mtu//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness)
self.comb += [
self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source)
]
# Wishbone interface
wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
for n in range(nrxslots)]
wb_tx_sram_ifs = [wishbone.SRAM(self.sram.reader.mems[n], read_only=False)
for n in range(ntxslots)]
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
wb_slaves = []
decoderoffset = log2_int(sram_depth, need_pow2=False)
decoderbits = log2_int(len(wb_sram_ifs))
for n, wb_sram_if in enumerate(wb_sram_ifs):
def slave_filter(a, v=n):
return a[decoderoffset:decoderoffset+decoderbits] == v
wb_slaves.append((slave_filter, wb_sram_if.bus))
self.submodules += wb_sram_if
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
self.submodules += wb_con
def __init__(self):
self.submodules.txmem = wishbone.SRAM(1024)
self.submodules.rxmem = wishbone.SRAM(1024)
self.sysbus = wishbone.Interface()
self.submodules.decoder = wishbone.Decoder(self.sysbus, [
(mem_decoder(0x1000, 1024), self.txmem.bus),
(mem_decoder(0x2000, 1024), self.rxmem.bus),
],
register=True)
self.bus = wishbone.Interface()
self.submodules.dma = DMATest()
self.submodules.arbiter = wishbone.Arbiter(
[self.bus, self.dma.master_bus], self.sysbus)
def __init__(self):
self.wb16 = wishbone.Interface(data_width=16)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb16, wb32)
self.submodules += up_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
def __init__(self, with_ethernet=False):
platform = Platform()
sys_clk_freq = int(1e6)
SoCCore.__init__(
self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv",
cpu_variant="linux",
with_uart=False,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x02000000, # 32MB
integrated_main_ram_init=get_mem_data(
{
"buildroot/Image": "0x00000000",
"buildroot/rootfs.cpio": "0x00800000",
"buildroot/rv32.dtb": "0x01000000"
}, "little"))
self.add_constant("SIM", None)
# supervisor
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# crg
self.submodules.crg = CRG(platform.request("sys_clk"))
# machine mode emulator ram
emulator_rom = get_mem_data("emulator/emulator.bin", "little")
self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"])
# serial
self.submodules.uart_phy = uart.RS232PHYModel(
platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# ethernet
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.submodules.ethmac = ethmac
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]),
self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
def __init__(self, platform, *args, gdbstub_rom_size=0x2000, **kwargs):
SoCSDRAM.__init__(self, platform, *args,
cpu_debug_address=self.mem_map["gdbstub_rom"],
csr_data_width=32,
**kwargs)
# gdbstub rom
self.gdbstub_rom_size = gdbstub_rom_size
self.submodules.gdbstub_rom = wishbone.SRAM(self.gdbstub_rom_size, read_only=True)
self.register_mem(
"gdbstub_rom", self.mem_map["gdbstub_rom"],
self.gdbstub_rom.bus, self.gdbstub_rom_size
)
self.submodules.uartdbg_phy = RS232PHY(platform.request("serial", 1),
self.clk_freq, self.uart_baudrate)
self.submodules.uartdbg = UART(self.uartdbg_phy)
# break button
prv = Signal(1, reset=1)
button = platform.request('user_btn', 0)
self.sync += [
prv.eq(button),
If(button & ~prv,
self.cpu_or_bridge.ext_break.eq(1),
).Else(
self.cpu_or_bridge.ext_break.eq(0),
)
]
def __init__(self, **kwargs):
super().__init__(**kwargs)
self.platform.add_extension(ltc.ltc_pads)
self.submodules.lvds = LTCPhy(self.platform, self.sys_clk_freq, 120e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.lvds.pads_dco)
# Frequency counter for received sample clock
self.submodules.f_sample = FreqMeter(self.sys_clk_freq)
self.comb += self.f_sample.clk.eq(ClockSignal("sample"))
spi_pads = self.platform.request("LTC_SPI")
self.submodules.spi = spi.SPIMaster(spi_pads, 16, self.sys_clk_freq,
self.sys_clk_freq / 32)
width, depth = 16 * 2, 8192
storage = Memory(width, depth, init=[0x1234, 0xCAFECAFE, 0x00C0FFEE])
self.specials += storage
self.submodules.adc_data_buffer = wishbone.SRAM(storage,
read_only=True)
port = storage.get_port(write_capable=True, clock_domain="sample")
self.register_mem("adc_data_buffer", 0x10000000,
self.adc_data_buffer.bus, depth * 8)
self.specials += port
self.submodules.acq = DumpToRAM(width, depth, port)
self.sync.sample += self.acq.adc_data.eq(
Cat(Signal(2), self.lvds.sample_outs[0], Signal(2),
self.lvds.sample_outs[1]))
self.sync += self.lvds.init_running.eq(self.ctrl.reset)
for p in LTCSocDev.csr_peripherals:
self.add_csr(p)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
if 'integrated_main_ram_size' not in kwargs:
kwargs['integrated_main_ram_size'] = 0x20000
clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model,
debug=False,
loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model,
mac_address,
ip_address,
debug=False)
self.submodules.ip_model = ip.IP(self.mac_model,
mac_address,
ip_address,
debug=False,
loopback=False)
self.submodules.udp_model = udp.UDP(self.ip_model,
ip_address,
debug=False,
loopback=False)
self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model,
debug=False)
self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address,
ip_address, 100000)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 0x1234)
self.submodules.sram = wishbone.SRAM(1024)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.etherbone.wishbone.bus, self.sram.bus)
def __init__(self):
self.wb32 = wishbone.Interface(data_width=32)
wb64 = wishbone.Interface(data_width=64)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb32, wb64)
down_converter = wishbone.DownConverter(wb64, wb32)
self.submodules += up_converter, down_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
def __init__(self):
self.axi = AXIInterface(data_width=32, address_width=32, id_width=8)
self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
axi2wishbone = AXI2Wishbone(self.axi, self.wishbone)
self.submodules += axi2wishbone
wishbone_mem = wishbone.SRAM(1024, bus=self.wishbone)
self.submodules += wishbone_mem
def __init__(self):
self.submodules.host = Host(64, root_id, endpoint_id,
phy_debug=False,
chipset_debug=False,
host_debug=False)
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy)
self.submodules.wishbone_bridge = LitePCIeWishboneBridge(self.endpoint, lambda a: 1)
self.submodules.sram = wishbone.SRAM(1024, bus=self.wishbone_bridge.wishbone)
def add_ram(self, name, origin, size, contents=[], mode="rw"):
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
ram = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name),
colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
def __init__(self, **kwargs):
soc_cls.__init__(self,
cpu_type="vexriscv",
cpu_variant="linux",
**kwargs)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
sys_clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
# TODO: Add SPI Flash support here.
# Support for soft-emulation for full Linux support ----------------------------------------
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
def __init__(self, **kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
SoCCore.__init__(
self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv",
cpu_variant="linux",
with_uart=False,
integrated_rom_size=0xC000,
integrated_main_ram_size=0x02000000, # 32MB
**kwargs)
# supervisor
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# crg
self.submodules.crg = CRG(platform.request("sys_clk"))
# machine mode emulator ram
emulator_rom = get_mem_data("emulator/emulator.bin", "little")
self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"])
# serial
self.submodules.uart_phy = uart.RS232PHYModel(
platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Integrate Adder8
self.submodules.adder8 = Adder8()
self.add_csr("adder8", 10, allow_user_defined=True)
# Integrate CAN
# self.submodules.can_ctrl = can_ctrl = SJA1000(platform.request("canif", 0))
# self.add_csr("can_ctrl", 11, allow_user_defined=True)
# self.add_interrupt("can_ctrl", 6, allow_user_defined=True)
# self.register_mem("can_ctrl", 0x30000000, can_ctrl.bus, 512)
# can_ctrl.add_source(platform)
# platform.add_verilog_include_path("periphs/verilog/can")
# Integrate SPI master
self.submodules.spi_master = spi_master = SpiMaster(
self.platform.request("spi", 0))
self.add_csr("spi_master", 11, allow_user_defined=True)
self.add_interrupt("spi_master", 6, allow_user_defined=True)
self.register_mem("spi_master", 0x30000000, spi_master.bus, 32)
spi_master.add_source(self.platform)
platform.add_verilog_include_path("periphs/verilog/spi")
def __init__(self,**kwargs):
soc_cls.__init__(self,
cpu_type="vexriscv",
cpu_variant="secure",
max_sdram_size=0x10000000, # Limit mapped SDRAM to 256MB for now
**kwargs)
self.platform.add_extension(arty_platform._i2s_pmod_io)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000)
soc_cls.mem_map.update(self.mem_map)
def __init__(self, cpu_variant="linux", uart_baudrate=1e6, **kwargs):
soc_cls.__init__(
self,
cpu_type="vexriscv",
cpu_variant=cpu_variant,
uart_baudrate=uart_baudrate,
max_sdram_size=0x10000000, # Limit mapped SDRAM to 256MB for now
**kwargs)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
def __init__(self,
platform,
clk_freq=int(166e6),
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
# Serial Wishbone Bridge
serial_bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.submodules += serial_bridge
self.add_wb_master(serial_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# Ethernet PHY and UDP/IP stack
self.submodules.ethphy = ethphy = LiteEthPHY(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
clk_freq=clk_freq)
self.add_csr("ethphy")
self.submodules.ethcore = ethcore = LiteEthUDPIPCore(
phy=ethphy,
mac_address=mac_address,
ip_address=ip_address,
clk_freq=clk_freq)
self.add_csr("ethcore")
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.crg.cd_sys.clk.attr.add("keep")
ethphy.crg.cd_eth_rx.clk.attr.add("keep")
ethphy.crg.cd_eth_tx.clk.attr.add("keep")
platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
ethphy.crg.cd_eth_rx.clk,
ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, with_analyzer=False):
clk_freq = int(125e6)
SoCCore.__init__(
self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Sayma RTM / AMC <--> RTM SERWB Link Test Design ",
ident_version=True,
with_timer=False)
self.submodules.crg = _CRG(platform)
# uart <--> wishbone
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# amc rtm link
serwb_phy = SERWBPHY(platform.device,
platform.request("serwb"),
mode="slave")
platform.add_period_constraint(
platform.lookup_request("serwb").clk_p, 10.)
self.submodules.serwb_phy = serwb_phy
self.comb += self.crg.serwb_refclk.eq(serwb_phy.serdes.clocking.refclk)
# wishbone master
serwb_core = SERWBCore(serwb_phy, clk_freq, mode="master")
self.submodules += serwb_core
self.add_wb_master(serwb_core.etherbone.wishbone.bus)
# wishbone test memory
self.submodules.serwb_sram = wishbone.SRAM(
8192, init=[i for i in range(8192 // 4)])
self.register_mem("serwb_sram", self.mem_map["serwb"],
self.serwb_sram.bus, 8192)
if with_analyzer:
activity = Signal()
self.comb += activity.eq(serwb_phy.serdes.decoders[0].d != 0)
analyzer_signals = [
activity, serwb_core.etherbone.wishbone.bus,
serwb_phy.serdes.rx_ce, serwb_phy.serdes.rx_k,
serwb_phy.serdes.rx_d, serwb_phy.serdes.tx_ce,
serwb_phy.serdes.tx_k, serwb_phy.serdes.tx_d
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 256)
def __init__(self):
SimSoC.__init__(self, cpu_type=None)
# ----------------------------
# memory to test
# ----------------------------
mem = Memory(32, 4096 // 2, init=[1, 0xDEAD, 0xBEEF, 0xC0FE, 0xAFFE])
self.specials += mem
self.submodules.sample_ram = wishbone.SRAM(mem)
self.register_mem(
"sram",
0x10000000, # [bytes]
self.sample_ram.bus,
mem.depth * 4 # [bytes]
)
def __init__(self):
self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
# # #
axi = AXILiteInterface(data_width=32, address_width=32)
wb = wishbone.Interface(data_width=32, adr_width=30)
wishbone2axi = Wishbone2AXILite(self.wishbone, axi)
axi2wishbone = AXILite2Wishbone(axi, wb)
self.submodules += wishbone2axi, axi2wishbone
sram = wishbone.SRAM(1024, init=[0x12345678, 0xa55aa55a])
self.submodules += sram
self.comb += wb.connect(sram.bus)
def __init__(self,
platform,
clk_freq=166 * 1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
clk_freq=clk_freq)
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
convert_ip(ip_address),
clk_freq)
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
def __init__(self, **kwargs):
soc_cls.__init__(self,
cpu_type="vexriscv",
cpu_variant="lite",
**kwargs)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
# Integrate int module
self.submodules.gpio_isr = GpioISR(self.platform.request('key', 0),
rissing_edge_detect=False)
self.add_csr("gpio_isr", 10, allow_user_defined=True)
self.add_interrupt("gpio_isr", 2, allow_user_defined=True)
def add_xram(self, name, origin, mem):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
ram = wishbone.SRAM(mem, bus=ram_bus)
self.bus.add_slave(
name, ram.bus,
SoCRegion(origin=origin,
size=mem.width * mem.depth,
mode='rw'))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
return
def add_memory(self, mem, *, name, origin, mode='rw'):
ram = wishbone.SRAM(mem,
bus=wishbone.Interface(data_width=mem.width),
read_only='w' not in mode)
# Perform bus width conversion
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(ram_bus, ram.bus)
# Add memory region
region = SoCRegion(origin=origin,
size=mem.width // 8 * mem.depth,
mode=mode)
self.bus.add_slave(name, ram_bus, region)
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [gmii_rst_n.eq(1)]
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
# sdram
sdram_module = MT47H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram_b"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, **kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
SoCCore.__init__(
self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv",
cpu_variant="linux",
with_uart=False,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x02000000, # 32MB
integrated_main_ram_init=get_mem_data(
{
"buildroot/Image": "0x00000000",
"buildroot/rootfs.cpio": "0x00800000",
"buildroot/rv32.dtb": "0x01000000"
}, "little"),
**kwargs)
self.cpu.use_external_variant("VexRiscv.v")
# supervisor
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# crg
self.submodules.crg = CRG(platform.request("sys_clk"))
# machine mode emulator ram
emulator_rom = get_mem_data("emulator/emulator.bin", "little")
self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"])
# serial
self.submodules.uart_phy = uart.RS232PHYModel(
platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
def __init__(self, platform, csr_data_width=8, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
csr_data_width=csr_data_width,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
# sdram
sdram_module = K4B2G1646F(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
clk_freq = (31 + Fraction(1, 4))*1000*1000
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size)
# sdram
if not self.integrated_main_ram_size:
sdram_module = MT46H32M16(clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1"
)
self.add_csr("ddrphy")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True)
)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self):
arty.EthernetSoC.__init__(self,
cpu_type="vexriscv",
cpu_variant="linux")
self.cpu.use_external_variant("VexRiscv.v")
self.add_constant("NETBOOT_LINUX_VEXRISCV", None)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
# spiflash
spiflash_pads = self.platform.request("spiflash4x")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=11,
div=2,
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
0x1000000)
self.add_constant("FLASHBOOT_LINUX_VEXRISCV", None)
self.add_constant("FLASH_BOOT_ADDRESS", None)