def add_csr_bridge(self, origin):
self.submodules.csr_bridge = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=self.csr.address_width,
data_width=self.csr.data_width))
csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region)
self.csr.add_master(name="bridge", master=self.csr_bridge.csr)
self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def __init__(
self,
platform,
clk_freq,
# CPU parameters
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
# ROM parameters
integrated_rom_size=0,
integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096,
integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0,
integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8,
csr_alignment=32,
csr_address_width=14,
# Identifier parameters
ident="",
ident_version=False,
# UART parameters
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True,
wishbone_timeout_cycles=1e6,
**kwargs):
self.platform = platform
self.clk_freq = clk_freq
# SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
self.soc_io_regions = self.io_regions
# SoC's Config/Constants/Regions
self.config = {}
self.constants = {}
self.mem_regions = {}
self.csr_regions = {}
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
self.add_retro_compat(kwargs)
# Parameters managment ---------------------------------------------------------------------
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(
cpu_variant.split('+')[0]).upper()
# Check type
if cpu_type not in cpu.CPUS.keys():
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add the CPU
self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant))
# Update Memory Map (if defined by CPU)
self.soc_mem_map.update(self.cpu.mem_map)
# Update IO Regions (if defined by CPU)
self.soc_io_regions.update(self.cpu.io_regions)
# Set reset address
self.cpu.set_reset_address(
self.soc_mem_map["rom"]
if integrated_rom_size else cpu_reset_address)
self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
# Add CPU buses as 32-bit Wishbone masters
for cpu_bus in self.cpu.buses:
assert cpu_bus.data_width in [32, 64, 128]
soc_bus = wishbone.Interface(data_width=32)
self.submodules += wishbone.Converter(cpu_bus, soc_bus)
self.add_wb_master(soc_bus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU interrupts
for _name, _id in self.cpu.interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
else:
self.add_cpu(cpu.CPUNone())
self.soc_io_regions.update(self.cpu.io_regions)
# Add user's interrupts (needs to be done after CPU interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + get_version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
csr_alignment = max(csr_alignment, self.cpu.data_width)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=csr_address_width,
data_width=csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone, 0x1000000)
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_baudrate=115200,
ident="",
with_timer=True):
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if with_uart:
self.submodules.uart_phy = uart.RS232PHY(
platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
if ident:
self.submodules.identifier = identifier.Identifier(ident)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
cpu_variant=None,
integrated_rom_size=0,
integrated_rom_init=[],
integrated_sram_size=4096,
integrated_main_ram_size=0,
integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
ident="",
ident_version=False,
reserve_nmi_interrupt=True,
with_timer=True):
self.config = dict()
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
self.cpu_variant = cpu_variant
if integrated_rom_size:
cpu_reset_address = self.mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address,
self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if reserve_nmi_interrupt:
self.soc_interrupt_map[
"nmi"] = 0 # Reserve zero for "non-maskable interrupt"
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
#else:
# del self.soc_interrupt_map["uart"]
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
else:
del self.soc_interrupt_map["timer0"]
# Invert the interrupt map.
interrupt_rmap = {}
for mod_name, interrupt in self.interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with user defined %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
interrupt_rmap[interrupt] = mod_name
# Add the base SoC's interrupt map
for mod_name, interrupt in self.soc_interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with SoC inbuilt %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
self.interrupt_map[mod_name] = interrupt
interrupt_rmap[interrupt] = mod_name
# Make sure other functions are not using this value.
self.soc_interrupt_map = None
# Make the interrupt vector read only
self.interrupt_map = ReadOnlyDict(self.interrupt_map)
# Save the interrupt reverse map
self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# FIXME: RocketChip reserves the first 256Mbytes for internal use
# remap rom to 0x10000000, sram to 0x20000000
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x20000000
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
# Support the old style which used underscore for separator
if cpu_variant is None:
cpu_variant = "standard"
cpu_variant = cpu_variant.replace('_', '+')
# Check for valid CPU variants.
cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
for key, values in CPU_VARIANTS.items():
if cpu_variant_processor not in [key,]+values:
continue
self.cpu_variant = key
break
else:
raise InvalidCPUVariantError(cpu_variant)
# Check for valid CPU extensions.
for ext in sorted(cpu_variant_ext):
if ext not in CPU_VARIANTS_EXTENSIONS:
raise InvalidCPUExtensionError(cpu_variant)
self.cpu_variant += "+"+ext
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add Wishbone to CSR bridge
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_alignment=32, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True, wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# NOTE: RocketChip reserves the first 256Mbytes for internal use,
# so we must change default mem_map;
# Also, CSRs *must* be 64-bit aligned.
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x11000000
self.soc_mem_map["csr"] = 0x12000000
csr_alignment = 64
# Mainline Linux OpenRISC arch code requires Linux kernel to be loaded
# at the physical address of 0x0. As we are running Linux from the
# MAIN_RAM region - move it to satisfy that requirement.
if cpu_type == "mor1kx" and cpu_variant == "linux":
self.soc_mem_map["main_ram"] = 0x00000000
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x50000000
self.soc_mem_map["csr"] = 0x60000000
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert csr_alignment in [32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = self.csr_data_width
self.config["CSR_ALIGNMENT"] = self.csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(
address_width=self.csr_address_width,
data_width=self.csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
def __init__(self,
platform,
clk_freq,
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
integrated_rom_size=0,
integrated_rom_init=[],
integrated_sram_size=4096,
integrated_sram_init=[],
integrated_main_ram_size=0,
integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
ident="",
ident_version=False,
wishbone_timeout_cycles=1e6,
with_timer=True,
with_ctrl=True):
self.config = dict()
self.platform = platform
self.clk_freq = clk_freq
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# FIXME: RocketChip reserves the first 256Mbytes for internal use
# remap rom to 0x10000000, sram to 0x20000000
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x20000000
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
# Support the old style which used underscore for separator
if cpu_variant is None:
cpu_variant = "standard"
cpu_variant = cpu_variant.replace('_', '+')
# Check for valid CPU variants.
cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
for key, values in CPU_VARIANTS.items():
if cpu_variant_processor not in [
key,
] + values:
continue
self.cpu_variant = key
break
else:
raise InvalidCPUVariantError(cpu_variant)
# Check for valid CPU extensions.
for ext in sorted(cpu_variant_ext):
if ext not in CPU_VARIANTS_EXTENSIONS:
raise InvalidCPUExtensionError(cpu_variant)
self.cpu_variant += "+" + ext
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.wishbone_timeout_cycles = wishbone_timeout_cycles
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
self._csr_masters = []
# add user csrs
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu(
lm32.LM32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(
mor1kx.MOR1KX(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(
picorv32.PicoRV32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(
vexriscv.VexRiscv(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(
minerva.Minerva(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(
rocket.RocketRV64(platform, self.cpu_reset_address,
self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_csr("cpu", allow_user_defined=True)
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# add cpu reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# add user interrupts
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone)
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
