def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(100e6),
integrated_rom_size=0x8000,
**kwargs):
platform = nexys4ddr.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT47H64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_vga=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# VGA terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
