HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1'
print '\nStarting client'
client = MemClient(host=HOST)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
start_time = time.time()
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE,
((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
LTC6954_configure(client)
# Set Mux for filtered data
# Set Dac A for SIN and Dac B for LUT
client.reg_write(
DATAPATH_CONTROL_BASE, DC2390_FIFO_ADCA_FIL | DC2390_DAC_B_NCO_COS
| DC2390_DAC_A_NCO_SIN | DC2390_LUT_ADDR_COUNT | DC2390_LUT_RUN_CONT)
ltc2500_cfg_led_on = ((LTC2500_DF_64 | LTC2500_SSCIN_FLAT_FILT) <<
6) | 0x03 | (LTC2500_N_FACTOR << 16)
ltc2500_cfg_led_off = (
(LTC2500_DF_64 | LTC2500_SSCIN_FLAT_FILT) << 6) | (LTC2500_N_FACTOR << 16)
client.reg_write(LED_BASE, ltc2500_cfg_led_on)
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
else:
print "Correct bitstream file found !!"
# Initialize the FPGA
#--------------------------------------------------------------------------
print("Setting up system parameters.\n")
# Set the LTC695 to 50 MHz
DC2390.LTC6954_configure(client, 0x04)
# Set the clock divider
# client.reg_write(DC2390.SYSTEM_CLOCK_BASE, 0xF5000000 | SYSTEM_CLOCK_DIVIDER) # Approx. 400ms sinc period
# client.reg_write(DC2390.SYSTEM_CLOCK_BASE, 0xFA800000 | SYSTEM_CLOCK_DIVIDER) # Approx. 200ms sinc period
client.reg_write(DC2390.SYSTEM_CLOCK_BASE, 0xFDFF0000
| SYSTEM_CLOCK_DIVIDER) # Approx. 200ms sinc period
# Set the sample depth
client.reg_write(DC2390.NUM_SAMPLES_BASE, NUM_SAMPLES)
# Configure the LTC2500
ltc2500_cfg_led_on = (((df | filt)) | 0x03 |
(DC2390.LTC2500_N_FACTOR << 16))
ltc2500_cfg_led_off = (((df | filt)) | (DC2390.LTC2500_N_FACTOR << 16))
client.reg_write(DC2390.LED_BASE, ltc2500_cfg_led_on)
sleep(0.1)
client.reg_write(DC2390.LED_BASE, ltc2500_cfg_led_off)
sleep(0.1)
# Start the application test
start_time = time.time()
print('Starting client')
client = MemClient(host=HOST)
#Read FPGA type and revision. This inherently checks the reg_read function
# (see type_rev_check function definition)
# Arguments are client (of course), expected FPGA load type, and minimum revision
if demo_board == 2512:
type_rev_check(client, 0x0001, 0x0104)
elif demo_board == 2390:
type_rev_check(client, 0xABCD, 0x1246)
# If we're using a DC2390, need to configure clocks
LTC6954_configure(client)
# And configure sample rate.
client.reg_write(SYSTEM_CLOCK_BASE, 99) # 50MHz / (99 + 1) = 500ksps
print('Okay, now lets blink some lights and run some tests!!')
client.reg_write(LED_BASE, 0x01) # Blink a light.
sleep(0.1)
client.reg_write(LED_BASE, 0x00)
sleep(0.1)
# Capture data!
xfer_start_time = time.time()
if (internal_ramp == True): # Using internal ramp generator, as opposed to
client.reg_write(DATAPATH_CONTROL_BASE,
RAMP_DATA) # external DC2512 test jig
else:
HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1'
print '\nStarting client'
client = MemClient(host=HOST)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
start_time = time.time()
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE,
((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_NYQ_SAMPLES)
LTC6954_configure(client)
LTC2758_write(client, LTC2748_DAC_A | LTC2758_WRITE_CODE_UPDATE_ALL,
2**17) #Set DACs to half scale on 0-5V range
LTC2758_write(client, LTC2748_DAC_B | LTC2758_WRITE_CODE_UPDATE_ALL, 2**17)
###########################
# Set Mux for Nyquist data
###########################
client.reg_write(
DATAPATH_CONTROL_BASE,
DC2390_FIFO_ADCA_NYQ | # DC2390_FIFO_ADCB_FIL or DC2390_FIFO_ADCB_NYQ
tuning_word = int(cycles_per_dac_sample * 2**nco_word_width)
print("Tuning Word:" + str(tuning_word))
print('Starting client')
client = MemClient(host=HOST)
#First thing's First!! Configure clocks...
LTC6954_configure(client)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print('FPGA load type ID: %04X' % type_id)
print('FPGA load revision: %04X' % rev)
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER)
client.reg_write(SYSTEM_CLOCK_BASE,
(LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
client.reg_write(PID_KP_BASE, PID_KP)
client.reg_write(PID_KI_BASE, PID_KI)
client.reg_write(PID_KD_BASE, PID_KD)
client.reg_write(PULSE_LOW_BASE, PULSE_LOW)
client.reg_write(PULSE_HIGH_BASE, PULSE_HIGH)
client.reg_write(PULSE_VAL_BASE, PULSE_VAL)
LTC6954_configure(client)
#datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select
#lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000
# DAC A:
# light on. reg_write takes the register address as the first argument, and the
# value to write as the second argument.
#tuning_word = 1 * 214748365 # 2 * 500kHz
player_0 = 1.136 #MHz
player_1 = 1.000 #MHz
player_2 = 0.893 #MHz
channel = player_2
fs = 10000000
f = channel * 1000000
tuning_word = int((f / fs) * 2**32) #429496730 # 1MHz
client.reg_write(TUNING_WORD_BASE, tuning_word) # Tune radio
client.reg_write(VOLUME_BASE, 254) # Set volume
print('Okay, now lets blink some lights!!')
for i in range(0, 2):
client.reg_write(LED_BASE,
0x00000001) # The line that actually talks to the FPGA
sleep(0.5)
client.reg_write(LED_BASE,
0x00000000) # The line that actually talks to the FPGA
sleep(0.5)
# Capture a sine wave
client.reg_write(DATAPATH_CONTROL_BASE, 0x00000000) # First capture ADC A
data = sockit_uns32_to_signed32(
sockit_capture(client, NUM_SAMPLES, trigger=0, timeout=2.0))
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print ('FPGA load type ID: %04X' % type_id)
print ('FPGA load revision: %04X' % rev)
LUT_DIVIDER = 0xC000 # Let's start with half-depth...
SYSTEM_CLOCK_DIVIDER = 1250
fb_gain = 0x5000
echo_gain = 0x7FF0
#fb_factor = 0xC000 #-4000
print("Setting up datapath...\n");
client.reg_write(SYSTEM_CLOCK_BASE, ((LUT_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
# The following routines read and write registers in the FPGA. These can be
# either read or write (or both), depending on the exact design.
# But fundamentally, when reading or writing a register from a script such as
# this one, you are reading or setting the state of a signal in the FPGA design.
# The addresses of the registers we will be talking to are defined in
# DC2390_functions.py, imported above. If you open it up, you will see these lines:
#
REV_ID_BASE = 0x10
LED_BASE = 0x40
number_of_reads = 50
starting_address = reg_address
reg_values = []
mem_values = []
for i in range(0, number_of_writes):
reg_values.append(i * 2)
mem_values.append(i * 2)
i2c_output_base_reg = 0x120
i2c_input_base_reg = 0x140
# Testing reg_write
if (verbose == True):
print 'Writing 0x%X to register 0x%X...' % (reg_value, reg_address)
written_address = client.reg_write(reg_address, reg_value, dummy)
if (written_address != reg_address):
print 'ERROR in Register Write. Returned wrong address.'
error = error + 1
# Testing reg_read
if (verbose == True): print 'Reading back register 0x%X...' % reg_address
reg_value_read = client.reg_read(reg_address, dummy)
if (verbose == True):
print 'Value at register 0x%X: 0x%X' % (reg_address, reg_value_read)
if (reg_value_read != reg_value):
print 'ERROR in Register Read. Returned wrong value.'
error = error + 1
print '** Tested Reg read and write. **\n'
sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1
) # 250ksps for 50M clock, 200 clocks per sample
cycles_per_sample = float(bin_number) / float(NUM_SAMPLES)
cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1)
tuning_word = int(cycles_per_dac_sample * 2**nco_word_width)
print("Tuning Word:" + str(tuning_word))
print('Starting client')
client = MemClient(host=HOST)
#First thing's First!! Configure clocks...
LTC6954_configure(client, 0x04)
#Read FPGA type and revision
type_rev_check(client, 0xABCD, 0x1246)
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER)
client.reg_write(SYSTEM_CLOCK_BASE,
(LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
client.reg_write(PID_KP_BASE, PID_KP)
client.reg_write(PID_KI_BASE, PID_KI)
client.reg_write(PID_KD_BASE, PID_KD)
client.reg_write(PULSE_LOW_BASE, PULSE_LOW)
client.reg_write(PULSE_HIGH_BASE, PULSE_HIGH)
client.reg_write(PULSE_VAL_BASE, PULSE_VAL)
#datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select
#lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000
# DAC A:
# .data0x ( nco_sin_out ),
# .data1x ( pid_output ),
start_time = time.time();
print('Starting client')
client = MemClient(host=HOST)
#Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print ('FPGA load type ID: %04X' % type_id)
print ('FPGA load revision: %04X' % rev)
if type_id != 0x0001:
print("FPGA type is NOT 0x0001! Make sure you know what you're doing!")
print ('Okay, now lets blink some lights and run some tests!!')
client.reg_write(LED_BASE, 0x01)
sleep(0.1)
client.reg_write(LED_BASE, 0x00)
sleep(0.1)
# Capture data!
xfer_start_time = time.time()
client.reg_write(DATAPATH_CONTROL_BASE, ADC_DATA) # First capture ADC A
data = sockit_uns32_to_signed32(sockit_capture(client, NUM_SAMPLES, edge = NEG, trigger = TRIG_NOW, timeout = 2.0))
data_ch0 = np.ndarray(NUM_SAMPLES, dtype=int)
data_ch1 = np.ndarray(NUM_SAMPLES, dtype=int)
if(numbits == 16):
for i in range(0, NUM_SAMPLES):
HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1'
print '\nStarting client'
client = MemClient(host=HOST)
# Read FPGA type and revision
rev_id = client.reg_read(REV_ID_BASE)
type_id = rev_id & 0x0000FFFF
rev = (rev_id >> 16) & 0x0000FFFF
print 'FPGA load type ID: %04X' % type_id
print 'FPGA load revision: %04X' % rev
start_time = time.time()
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE,
((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
# Set the LTC6954 to output 50 MHz
# Divisors of 5, 6 will give CLK frequencies of 40MHz, 33.3MHz. This may be
# useful for debugging FPGA timing.
LTC6954_configure(client, 4)
client.reg_write(
LED_BASE,
(LTC2500_DF_64 | LTC2500_SSCIN_FLAT_FILT)) # Initial LTC2500 SYNC
# Set Mux for filtered data
# Set Dac A for SIN and Dac B for LUT
client.reg_write(
DATAPATH_CONTROL_BASE, mux_port | DC2390_DAC_B_NCO_COS
| DC2390_DAC_A_NCO_SIN | DC2390_LUT_ADDR_COUNT | DC2390_LUT_RUN_CONT)
sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1
) # 250ksps for 50M clock, 200 clocks per sample
cycles_per_sample = float(bin_number) / float(NUM_SAMPLES)
cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1)
tuning_word = int(cycles_per_dac_sample * 2**nco_word_width)
print("Tuning Word:" + str(tuning_word))
print('Starting client')
client = MemClient(host=HOST)
#First thing's First!! Configure clocks...
LTC6954_configure(client, 0x04)
#Read FPGA type and revision
type_rev_check(client, 0xABCD, 0x1246)
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER)
client.reg_write(SYSTEM_CLOCK_BASE,
(LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
#datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select
#lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000
# DAC A:
# .data0x ( nco_sin_out ),
# .data1x ( pid_output ),
# .data2x ( 16'h4000 ),
# .data3x ( 16'hC000 ),
# DAC B:
# .data0x ( nco_cos_out ),
# .data1x ( lut_output ),
# .data2x ( 16'hC000 ),
sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1
) # 250ksps for 50M clock, 200 clocks per sample
cycles_per_sample = float(bin_number) / float(NUM_SAMPLES)
cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1)
tuning_word = int(cycles_per_dac_sample * 2**nco_word_width)
print("Tuning Word:" + str(tuning_word))
print('Starting client')
client = MemClient(host=HOST)
#First thing's First!! Configure clocks...
LTC6954_configure(client)
#Check FPGA type and revision
type_rev_check(client, 0xABCD, 0x1246)
print("Setting up system parameters.\n")
client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER)
client.reg_write(SYSTEM_CLOCK_BASE,
(LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER))
client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
pll_locked = client.reg_read(DATA_READY_BASE) # Check data ready signal
if ((pll_locked & 0x02) == 0x02):
print("PLL is LOCKED!")
else:
print("PLL is NOT locked, check power to DC2390")
#datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select
#lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000
# DAC A:
# .data0x ( nco_sin_out ),
# .data1x ( pid_output ),
rev_id = client.reg_read(
REV_ID_BASE) # The line that actually talks to the FPGA
type_id = rev_id & 0x0000FFFF # Extract the lower 16-bits
rev = (rev_id >> 16) & 0x0000FFFF # Extract the upper 16-bits.
print('FPGA load type ID: %04X' % type_id)
print('FPGA load revision: %04X' % rev)
# Next, we use the reg_write() function to blink a light! LED0 is connected to
# the least significant bit of register 0x40, and writing a "1" will turn the
# light on. reg_write takes the register address as the first argument, and the
# value to write as the second argument.
print('Okay, now lets blink some lights!!')
for i in range(0, 10):
client.reg_write(LED_BASE,
0x00000001) # The line that actually talks to the FPGA
sleep(0.5)
client.reg_write(LED_BASE,
0x00000000) # The line that actually talks to the FPGA
sleep(0.5)
# The next section shows how to properly shut down the SoCkit board. It's a
# Linux computer after all, with nonvolatile storage that should be unmounted
# cleanly. Just cutting the power will force a filesystem check (fsck) on the
# next boot. You can either set "choice = 'y'" below, or type
# "client.shutdown()" in the Python console
# What client.shutdown() really does is execute the command:
# "shutdown -h now"
# on the SoCkit board.