Ejemplo n.º 1
0
def example_1_truth_table():
	## Generate booleean logic combination for 3 input
	import itertools
	input_value = list(itertools.product([0, 1], repeat=3))

	print "Truth Table ----------------"

	for i in range (len(input_value)):

		## three input wires - for input to gate
		w1 = lg.Source("w1",pos=(0.5,0.1),in1=input_value[i][0])
		w2 = lg.Source("w2",pos=(0.5,-0.1),in1=input_value[i][1])
		w3 = lg.Source("w3",pos=(1.5,-0.1),in1=input_value[i][2])	     

		## sink for taking output
		sink = lg.Sink("sink",pos=(3,0))

		## two gates with delay
		g1 = lg.AndGate("and1",pos=(1,0),delay=2)       # gate delay
		g2 = lg.OrGate("or1",pos=(2,0))
		
		## Connectors and delay
		c1 = lg.Connector(w1,g1,1)		## wire1 to and1_A - wire delay 1
		c2 = lg.Connector(w2,g1,2)		## wire2 to and1_B - wire delay 2
		c3 = lg.Connector(g1,g2,3)		## and1_out to or1_A - wire delay 3
		c4 = lg.Connector(w3,g2,4) 		## wire3 to or1_B - wire delay 4
		c5 = lg.Connector(g2,sink)		## or1_out to sink 

		print "{} {} {} - {}".format(input_value[i][0], input_value[i][1], input_value[i][2], sink.getGateOutput())
Ejemplo n.º 2
0
def check_not():
    input_value = (0, 1)
    print "Not Gate"
    for i in range(len(input_value)):
        w1 = lg.Source("w1", input_value[i])
        w3 = lg.Sink("sink")

        g1 = lg.NotGate("notGate1")

        c1 = lg.Connector(w1, g1)
        c3 = lg.Connector(g1, w3)
        print "{} - {}".format(input_value[i], w3.getGateOutput())
    print "Done-----------------"
Ejemplo n.º 3
0
def example_2_truth_table():
	## Generate booleean logic combination for 3 input
	import itertools
	input_value = list(itertools.product([0, 1], repeat=3))

	print "Truth Table ----------------"

	for i in range (len(input_value)):

		w1 = lg.Source("w1",pos=(0,0.1),in1=input_value[i][0])
		w2 = lg.Source("w2",pos=(0,0),in1=input_value[i][1])
		w3 = lg.Source("w3",pos=(1,-0.1),in1=input_value[i][2])

		sink = lg.Sink("sink",pos=(3,0))

		g1 = lg.AndGate("and1",pos=(1.5,0.5),delay=2)       # gate delay
		g2 = lg.NotGate("not1",pos=(1,0),delay=2)       # gate delay
		g3 = lg.OrGate("or1",pos=(2,0),delay=1)
		g4 = lg.AndGate("and2",pos=(2.5,0),delay=2)       # gate delay
		    
		c1 = lg.Connector(w1,g1,0.15)   # wire to and1_A       # wire delay
		c2 = lg.Connector(w2,g2,0.1)	# wire to not_in
		c3 = lg.Connector(w3,g3,0.1)	# wire to or_A
		c4 = lg.Connector(g2,g1,0.1)	# not_out to and1_B
		c5 = lg.Connector(g2,g3,0.3)	# not_out to or_B
		c6 = lg.Connector(g1,g4,0.2)	# and1_out to and2_A
		c7 = lg.Connector(g3,g4,0.25)	# or_out to and2_B
		c8 = lg.Connector(g4,sink)		# and2_out to sink

		print "{} {} {} - {}".format(input_value[i][0], input_value[i][1], input_value[i][2], sink.getGateOutput())
Ejemplo n.º 4
0
def check_and():
    input_value = ([0, 0], [0, 1], [1, 0], [1, 1])
    print "AND Gate"
    for i in range(len(input_value)):
        w1 = lg.Source("w1", input_value[i][0])
        w2 = lg.Source("w2", input_value[i][1])
        w3 = lg.Sink("sink")

        g1 = lg.AndGate("andGate1")

        c1 = lg.Connector(w1, g1)
        c2 = lg.Connector(w2, g1)
        c3 = lg.Connector(g1, w3)
        print "{} {} - {}".format(input_value[i][0], input_value[i][1],
                                  w3.getGateOutput())
    print "Done-----------------"
Ejemplo n.º 5
0
def check_nor():
    input_value = ([0, 0], [0, 1], [1, 0], [1, 1])
    print "NOR Gate"
    for i in range(len(input_value)):
        w1 = lg.Source("w1", input_value[i][0])
        w2 = lg.Source("w2", input_value[i][1])
        w3 = lg.Sink("sink")

        g1 = lg.OrGate("orGate1")
        g2 = lg.NotGate("ng1")

        c1 = lg.Connector(w1, g1)
        c2 = lg.Connector(w2, g1)
        c3 = lg.Connector(g1, g2)
        c4 = lg.Connector(g2, w3)
        print "{} {} - {}".format(input_value[i][0], input_value[i][1],
                                  w3.getGateOutput())
    print "Done-----------------"
Ejemplo n.º 6
0
def check_graph_plot():

    w1 = lg.Source("w1", pos=(0.5, 0.1))
    w2 = lg.Source("w2", pos=(0.5, -0.1))
    w3 = lg.Source("w3", pos=(1.5, -0.1))

    sink = lg.Sink("sink", pos=(3, 0))

    g1 = lg.AndGate("and1", pos=(1, 0), delay=2)  # gate delay
    g2 = lg.AndGate("or1", pos=(2, 0))

    c1 = lg.Connector(w1, g1, 1)  # wire delay
    c2 = lg.Connector(w2, g1, 2)
    c3 = lg.Connector(g1, g2, 3)
    c4 = lg.Connector(w3, g2, 4)
    c5 = lg.Connector(g2, sink)

    # print "{} {} - {}".format(input_value[i][0], input_value[i][1], w3.getGateOutput())

    print "Done-----------------"

    lg.draw_gate_representation()
    # vertex,edge = lg.get_edge_vertex()
    vertex1, edge1 = lg.get_edge_vertex_for_delay_graph()
    Path_Dict = ap.path_calculculation(vertex1, edge1)
    print "Main Path Dict =", Path_Dict

    plot_delay_path(Path_Dict)

    # print "vertex ----"
    # print vertex
    # print "edge ----"
    # print edge
    # print lg.node_info
    print "edge delay----"
    print edge1

    print "vertex delay----"
    print vertex1

    lg.draw_delay_graph()
Ejemplo n.º 7
0
def example_1():	
	w1 = lg.Source("w1",pos=(0.5,0.1))
	w2 = lg.Source("w2",pos=(0.5,-0.1))
	w3 = lg.Source("w3",pos=(1.5,-0.1))

	sink = lg.Sink("sink",pos=(3,0))

	g1 = lg.AndGate("and1",pos=(1,0),delay=2)       # gate delay
	g2 = lg.OrGate("or1",pos=(2,0))
	    
	## Connectors and delay
	c1 = lg.Connector(w1,g1,1)		## wire1 to and1_A - wire delay 1
	c2 = lg.Connector(w2,g1,2)		## wire2 to and1_B - wire delay 2
	c3 = lg.Connector(g1,g2,3)		## and1_out to or1_A - wire delay 3
	c4 = lg.Connector(w3,g2,4) 		## wire3 to or1_B - wire delay 4
	c5 = lg.Connector(g2,sink)		## or1_out to sink 

	## Draw Gate level representation 
	lg.draw_gate_representation()
    
    ## Draw delay graph and get edge and vertex
	lg.draw_delay_graph()
	vertex1,edge1 = lg.get_edge_vertex_for_delay_graph()

	# print "edge delay----"
	# print edge1

	# print "vertex delay----"
	# print vertex1

	## Path calculation
	Path_Dict=ap.path_calculculation (vertex1,edge1)
	print "Main Path Dict =",Path_Dict

    ## Plot critical path
	plot_delay_path(Path_Dict)
Ejemplo n.º 8
0
def example_2():
	w1 = lg.Source("w1",pos=(0,0.1))
	w2 = lg.Source("w2",pos=(0,0))
	w3 = lg.Source("w3",pos=(1,-0.1))

	sink = lg.Sink("sink",pos=(3,0))

	g1 = lg.AndGate("and1",pos=(1.5,0.5),delay=2)       # gate delay
	g2 = lg.NotGate("not1",pos=(1,0),delay=2)       # gate delay
	g3 = lg.OrGate("or1",pos=(2,0),delay=1)
	g4 = lg.AndGate("and2",pos=(2.5,0),delay=2)       # gate delay
	    
	c1 = lg.Connector(w1,g1,0.15)   # wire to and1_A       # wire delay
	c2 = lg.Connector(w2,g2,0.1)	# wire to not_in
	c3 = lg.Connector(w3,g3,0.1)	# wire to or_A
	c4 = lg.Connector(g2,g1,0.1)	# not_out to and1_B
	c5 = lg.Connector(g2,g3,0.3)	# not_out to or_B
	c6 = lg.Connector(g1,g4,0.2)	# and1_out to and2_A
	c7 = lg.Connector(g3,g4,0.25)	# or_out to and2_B
	c8 = lg.Connector(g4,sink)		# and2_out to sink
	## Draw Gate level representation 
	lg.draw_gate_representation()
	
	## Draw delay graph and get edge and vertex
	lg.draw_delay_graph()
	vertex1,edge1 = lg.get_edge_vertex_for_delay_graph()

	# print "edge delay----"
	# print edge1

	# print "vertex delay----"
	# print vertex1

	Path_Dict=ap.path_calculculation (vertex1,edge1)
	print "Main Path Dict =",Path_Dict

    ## Plot path
	plot_delay_path(Path_Dict)