def run(self):
if self.state == 'idle':
if self.queue != []:
self.Tms, self.Tdi, self.Catch = self.queue.pop(0)
if self.Tms == 'force':
veri.force(self.Tdi, str(self.Catch))
return
if self.Tms == 'label':
self.Catch.write('%s\n' % self.Tdi)
return
if self.Tms == 'finish':
logs.log_info('finishing from jtag sequence')
# self.Catch.write(self.Tdi)
veri.finish()
return
self.force(self.jtck, 0)
self.force(self.jtms, self.Tms)
self.force(self.jtdi, self.Tdi)
self.state = 'step0'
else:
self.force(self.jtck, 0)
self.force(self.jtms, 0)
self.force(self.jtdi, 0)
return
elif self.state == 'step0':
self.force(self.jtck, 1)
self.state = 'step1'
elif self.state == 'step1':
self.force(self.jtck, 0)
if self.Catch == 1:
self.responce = veri.peek(
'%s.%s' % (self.Path, self.jtdo)) + self.responce
elif self.Catch == 'x':
self.responce = 'X' + self.responce
elif self.responce != '':
(Cmd, Val, Len) = self.commands.pop(0)
RR = logs.intx(self.responce)
try:
logs.log_info('jtag RES 0x%x %s %x %s %x %s lastir=(%x)' %
(RR, self.responce, logs.intx(self.responce),
Cmd, Val, Len[0], Len[1]))
except:
logs.log_info('jtag RES 0x%x %s %s %s (x) %s lastir=(%s)' %
(RR, self.responce, Cmd, Val, Len, Len))
if self.callback:
self.callback(logs.intx(self.responce), Cmd, Val, Len)
self.responce = ''
else:
self.responce = ''
self.state = 'idle'
def bitarray2(self, Side):
Addr = logs.intx(veri.peek_mem('%s.paddress' % (self.Path), str(0)))
if Side == 'a':
if Addr in self.proga:
Text = self.proga[Addr]
else:
Text = ' a empty'
if Side == 'b':
if Addr in self.progb:
Text = self.progb[Addr]
else:
Text = ' b empty'
Dst = getDst(Text)
a_write_bits0_flag = self.peek('%s0_write_bits0_flag' % Side)
if a_write_bits0_flag == 1:
a0_dst_field = self.peek('%s0_dst_field' % Side)
if a0_dst_field > 0:
abitwdata = self.peek('bitfile.%sbitwdata' % Side)
if a0_dst_field not in self.Bits:
self.Bits[a0_dst_field] = -1
Var = self.Bits[a0_dst_field]
logs.log_info3(
'catchBitWrite side=%s dst=%d (%s) wdata=%s "%s"' %
(Side, a0_dst_field, Dst, abitwdata, Text))
Addr = logs.intx(veri.peek_mem('%s.paddress' % (self.Path), str(1)))
if Side == 'a':
if Addr in self.proga:
Text = self.proga[Addr]
else:
Text = ' a empty'
if Side == 'b':
if Addr in self.progb:
Text = self.progb[Addr]
else:
Text = ' b empty'
Dst = getDst(Text)
a_compare_valid = self.peek('%s_compare_valid' % Side)
if a_compare_valid == 1:
dst_field = self.peek('%s1_dst_field' % Side)
if dst_field > 0:
wdata = self.peek('%s_compare_out' % Side)
Var = self.Bits[dst_field]
logs.log_info3(
'catchBitWrite compare side=%s dst=%d (%s) wdata=%s "%s"'
% (Side, dst_field, Var, wdata, Text))
def run1(self):
if veri.peek('tb.dut.dig_top.usat_tx.enable') != '1': return
cnt = logs.peek('tb.dut.dig_top.usat_tx.serializer.cnt')
if cnt != 11: return
din0 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_0')
din1 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_1')
Chr0 = encdec_8b10b.trans10to8(din0)
Chr1 = encdec_8b10b.trans10to8(din1)
Chr0 = nice(Chr0)
Chr1 = nice(Chr1)
self.Stream[0].append(Chr0)
self.Stream[1].append(Chr1)
self.dins.append(
('%03x' % (logs.intx(din1)), '%03x' % (logs.intx(din0))))
if len(self.dins) > 8: self.dins.pop(0)
if len(self.Stream[0]) > 8: self.Stream[0].pop(0)
if len(self.Stream[1]) > 8: self.Stream[1].pop(0)
# if len(self.Stream[0])==8:
# logs.log_info('STREAM side0 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))
# logs.log_info('STREAM side1 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))
if syncAll(self.Stream[0]) and syncAll(self.Stream[1]):
self.syncState = 'idle'
if self.syncState == 'idle':
if sync8(self.Stream[0]) and sync8(self.Stream[1]):
self.syncState = 'sync8'
self.Stream[0] = []
self.Stream[1] = []
elif self.syncState == 'sync8':
if len(self.Stream[0]) == 8:
logs.log_info('STREAM8 %s %s' %
(self.Stream[1], self.Stream[0]))
# logs.log_info('STREAM8 X %s'%str(self.dins))
self.Stream[0] = []
self.Stream[1] = []
txc_0 = logs.peek('tb.dut.dig_top.usat_tx.txc_0')
txd_0 = logs.peek('tb.dut.dig_top.usat_tx.txd_0')
txc_1 = logs.peek('tb.dut.dig_top.usat_tx.txc_1')
txd_1 = logs.peek('tb.dut.dig_top.usat_tx.txd_1')
# logs.log_info('side0 %s %s %s %02x side1 %s %s %s %02x'%(din0,Chr0,self.txc_0,self.txd_0,din1,Chr1,self.txc_1,self.txd_1))
self.txc_0 = txc_0
self.txd_0 = txd_0
self.txc_1 = txc_1
self.txd_1 = txd_1
def use_command_wrds(self, wrds):
if wrds == []: return
if (wrds[0] in ['quit', 'exit']):
veri.finish()
elif wrds[0] in ['slow', 'sleep']:
if len(wrds) == 1:
veri.force('tb.run_slowly', '1')
elif wrds[1] in ['True', '1']:
veri.force('tb.run_slowly', '1')
elif wrds[1] in ['False', '0']:
veri.force('tb.run_slowly', '0')
else:
print 'command "slow" or "sleep" accept one parameter: True or False or 1 or 0"'
elif wrds[0] == 'os':
Cmd = string.join(wrds[1:], ' ')
os.system(Cmd)
elif wrds[0] == 'time':
print 'time', veri.stime()
elif wrds[0] == 'eval':
Cmd = string.join(wrds[1:], ' ')
print eval(Cmd)
elif wrds[0] == 'exec':
Cmd = string.join(wrds[1:], ' ')
exec(Cmd)
elif wrds[0] in ['file', 'source']:
try:
Fin = open(wrds[1])
except:
print 'failed to open %s' % wrds[1]
return
lines = Fin.readlines()
Fin.close()
for line in lines:
wrds0 = string.split(line)
print '>>', wrds0
use_command_wrds(self, wrds0)
elif (wrds[0] == 'clear'):
apb.wrqueue = []
elif (wrds[0] == 'history'):
for ind, X in enumerate(CommandsHistory):
print ind, X
elif (wrds[0] == 'reset'):
veri.force('tb.rst_n', '0')
apb.waiting = 20
elif (wrds[0] == 'listing'):
veri.listing('tb', '100', 'deep.list')
elif (wrds[0] == 'force'):
veri.force(wrds[1], wrds[2])
elif (wrds[0] == 'peek'):
Val = veri.peek(wrds[1])
logs.log_info('peeking %s 0x%x %s' %
(wrds[1], logs.intx(Val), Val))
elif (wrds[0] == 'apb'):
Addr = eval(wrds[1])
Data = eval(wrds[2])
apb.wrqueue.append((Addr, Data))
else:
print 'y ', HELP
def ram_operator(Id, Path):
PP = logs.bin2str(Path)
ID = logs.intx(Id)
# logs.log_info('ram_operator %s %s'%(PP,ID))
if (ID <= 0):
pass
elif ID not in ANTS:
ANTS[ID] = antClass.ramClass(PP, ID)
else:
ANTS[ID].run()
def run(self):
if self.Active:
self.Active = False
if self.Addr in self.Ram:
Rdata = self.Ram[self.Addr]
else:
Rdata = 0
self.force('outputs', bin(Rdata))
if self.Print:
logs.log_info('read ram %s [%x] -> %x' %
(self.Prefix, self.Addr, Rdata))
Access = self.peek('inputs')
Ceb = Access[-1]
Web = Access[-2]
Access = Access[:-2]
if self.Bweb:
Bweb = Access[-self.dataWidth:]
Access = Access[:-self.dataWidth]
else:
Bweb = '0' * self.dataWidth
Addr = logs.intx(Access[-self.addrWidth:])
Access = Access[:-self.addrWidth]
Wbits = logs.intx(Bweb)
Wdata = logs.intx(Access)
if (Web == '0') and (Ceb == '0'):
if Addr in self.Ram:
Rdata = self.Ram[Addr]
else:
Rdata = 0
newData = (~Wbits & Wdata) | ((Wbits) & Rdata)
self.Ram[Addr] = newData
if self.Print:
logs.log_info('write ram %s [%x] <= %x (%x&%x)|(%x&%x)' %
(self.Prefix, Addr, newData, Wdata, Wbits,
(~Wbits), Rdata))
elif (Web == '1') and (Ceb == '0'):
self.Active = True
self.Addr = Addr
return
def catching(self):
if self.Catch==1:
self.responce = str(self.peek(self.jtdo))+self.responce
# veri.force('tb.marker0',str(self.peek(self.jtdo)))
elif self.Catch=='x':
self.responce = 'X'+self.responce
elif self.responce!='':
(Cmd,Val,Len) = self.commands.pop(0)
self.RR = logs.intx(self.responce)
logs.log_info('END RR %s %x'%(self.responce,self.RR),2)
try:
logs.log_info('jtag RES 0x%x %s %x %s %x %s lastir=(%x)'%(self.RR,self.responce,logs.intx(self.responce),Cmd,Val,Len[0],Len[1]))
except:
logs.log_info('jtag RES 0x%x %s %s %s (x) %s lastir=(%s)'%(self.RR,self.responce,Cmd,Val,Len,Len))
if self.callback:
self.callback(logs.intx(self.responce),Cmd,Val,Len)
self.CHECKS.append(logs.intx(self.responce))
self.responce=''
else:
self.responce=''
def runRx(self):
if self.rxWaiting>0:
self.rxWaiting -= 1
return
if self.rxState=='idle':
Rxd = self.peek(self.txd)
if Rxd==0:
self.rxState='bit0'
self.rxWaiting = self.baudRate/2
return
elif self.rxState=='bit0':
self.rxState='bitx'
self.rxWaiting = self.baudRate
Rxd = self.peek(self.txd)
if Rxd!=0:
logs.log_error('ilia rxd start bit isnt there')
self.rxState='idle'
return
elif self.rxState=='bitx':
Rxd = self.peek(self.txd)
self.rxbyte = str(Rxd) + self.rxbyte
if len(self.rxbyte)==8:
self.rxState = 'stop'
# self.rxQueue.append(self.rxbyte)
Int = logs.intx(self.rxbyte)
if ((Int>=0)and(Int<256)):
Chr = chr(logs.intx(self.rxbyte))
else:
Chr = '(ERR%s)'%self.rxbyte
logs.log_info('uart rxbyte %s "%s" '%(self.rxbyte,Chr))
# veri.force('tb.marker','0b'+self.rxbyte)
self.rxbyte=''
self.rxWaiting = self.baudRate
elif self.rxState=='stop':
Rxd = self.peek(self.txd)
if Rxd==0:
logs.log_error('ilia rxd stop bit isnt there')
self.rxState='idle'
def monside(self, Side):
awrite = self.peek(Side + 'write')
if awrite == 1:
awdata = self.peek(Side + 'wdata')
awaddr = self.peek(Side + 'waddr')
done = False
Addr = 0
Cind = 0
Opcode = 0
for Ind in [6, 5, 3, 2, 1, 0]:
flagName = '%s%d_write_dst%d_flag' % (Side, Ind, Ind)
Flag = self.peek(flagName)
if Flag and not done:
done = True
Addr = logs.intx(
veri.peek_mem('%s.paddress' % (self.Path), str(Ind)))
Cind = Ind
if Ind > 0:
Opcode = logs.intx(
veri.peek_mem('%s.%sopcodes' % (self.Path, Side),
str(Ind - 1)))
else:
Opcode = logs.intx(
veri.peek_mem('%s.%sopcodes' % (self.Path, Side),
str(Ind)))
self.catchWrite(Side, awaddr, awdata, Addr, Opcode, Cind)
Cind = 0
reverse_awrite = self.peek('reverse_%swrite' % Side)
if reverse_awrite == 1:
awdata = self.peek('reverse_' + Side + 'wdata')
awaddr = self.peek('reverse_' + Side + 'waddr')
done = False
Addr = 0
for Ind in [0, 1, 2, 3, 5, 6]:
flagName = '%s%d_write_dst%d_flag' % (Side, Ind, Ind)
Flag = self.peek(flagName)
if Flag and not done:
done = True
Cind = Ind
Addr = logs.intx(
veri.peek_mem('%s.paddress' % (self.Path),
str(Ind)))
if Ind > 0:
Opcode = logs.intx(
veri.peek_mem(
'%s.%sopcodes' % (self.Path, Side),
str(Ind - 1)))
else:
Opcode = logs.intx(
veri.peek_mem(
'%s.%sopcodes' % (self.Path, Side),
str(Ind)))
self.catchWrite(Side, awaddr, awdata, Addr, Opcode, Cind)
def peek(Sig, Basex=Base, Bin=False):
if (',' in Sig) or (' ' in Sig):
Sig1 = string.replace(Sig, ',', ' ')
ww = string.split(Sig1)
res = []
for AA in ww:
Val = peek(AA, Basex, Bin)
res.append(Val)
return res
Full = '%s.%s' % (Basex, Sig)
if Full not in Values:
logs.log_error('sig %s not in path %s' % (Sig, Basex))
return -1
if Bin:
return Values[Full][0]
else:
return logs.intx(Values[Full][0])
def parseBin(Bin,Params,Signed=True):
Num = Params[0]
Len = len(Bin)
One = int(Len/Num)
LL = []
while Bin != '':
Head = Bin[:One]
Bin = Bin[One:]
if len(Params)==1:
if Signed:
Hsig = logs.intxsigned(Head)
if Hsig==9999:
logs.log_error('NNNNNNNN %s %s bin=%s params=%s'%(Head,Hsig,Bin,Params))
else:
Hsig = logs.intx(Head)
LL.append(Hsig)
else:
Lhd = parseBin(Head,Params[1:],Signed)
LL.append(Lhd)
return LL
def run(self):
if self.peek('rst_n') == 0:
self.reset()
return
if self.peek('write_tx') == 1:
txdata = self.peek('txdata')
self.txqueue.append(txdata)
if self.txstate == 'idle':
if self.txqueue != []:
self.txstate = 'work'
self.txstring = '11' + logs.binx(self.txqueue.pop(0)) + '0'
self.force('sending', bin(int(self.txstring[2:-1], 2)))
elif self.txstate == 'work':
self.force('txd', self.txstring[-1])
self.txstring = self.txstring[:-1]
self.txcount = 0
self.txstate = 'wait'
elif self.txstate == 'wait':
self.txcount += 1
if self.txcount == self.peek('baudrate'):
if self.txstring == '':
self.txstate = 'idle'
else:
self.txstate = 'work'
if self.txqueue == []:
self.force('tx_empty', 1)
else:
self.force('tx_empty', 0)
if (self.peek('read_rx') == 1) and (self.rxqueue != []):
self.rxqueue.pop(0)
if self.rxqueue == []:
self.force('rx_valid', 0)
if self.rxqueue != []:
self.force('rxdata', self.rxqueue[0])
self.force('rx_valid', 1)
# logs.asciiForce('tb.rxstate',self.rxstate)
# logs.asciiForce('tb.txstate',self.txstate)
if self.rxstate == 'idle':
rxd = self.peek('rxd')
if rxd == 0:
self.rxstate = 'open'
self.rxcount = 0
self.rxstring = ''
elif self.rxstate == 'open':
self.rxcount += 1
if self.rxcount == (self.peek('baudrate') / 2):
rxd = self.peek('rxd')
if rxd == 0:
self.rxstate = 'accumulate'
self.rxcount = 0
else:
self.rxstate = 'idle'
elif self.rxstate == 'accumulate':
self.rxcount += 1
if self.rxcount == (1 + self.peek('baudrate')):
self.rxstring = str(self.peek('rxd')) + self.rxstring
self.rxcount = 0
if len(self.rxstring) == 8:
self.rxstate = 'closing'
elif self.rxstate == 'closing':
self.rxcount += 1
if self.rxcount == (1 + self.peek('baudrate')):
if self.peek('rxd') == 0:
self.rxstate = 'badclosing'
logs.log_error('badclosing')
else:
Int = logs.intx(self.rxstring)
self.rxqueue.append(Int)
if not self.dump_lines:
logs.log_info('rx char %02x "%s"' % (Int, chr(Int)))
elif Int == ord('\n'):
Map = map(chr, self.rxqueue)
Str = string.join(Map, '')
logs.log_info('uartrx: %s' % Str)
self.rxqueue = []
self.rxcount = 0
self.rxstate = 'idle'
self.rxstring = ''
elif self.rxstate == 'badclosing':
self.rxcount += 1
if self.rxcount == (1 + self.peek('baudrate')):
self.rxcount = 0
self.rxstate = 'idle'
self.rxstring = ''
veri.force('tb.marker', str(len(self.rxstring)))
veri.force('tb.marker2', str(len(self.txstring)))
def blobrun(AA, Pin, Val):
colorlib.blobrun(logs.intx(AA), logs.intx(Pin), logs.intx(Val))
def colorrun(AA, Val):
colorlib.colorrun(logs.intx(AA), logs.intx(Val))
def floprun(AA, Pin, Val):
colorlib.floprun(logs.intx(AA), logs.intx(Pin), logs.intx(Val))
def peek_mem(self, Sig, Ind):
return logs.intx(veri.peek_mem('%s.%s' % (self.Path, Sig), str(Ind)))
def peek(self, Sig):
return logs.intx(self.peekbin(Sig))
def assign(self, Reg, Val):
Val = logs.intx(Val)
if Val != self.regs[Reg]:
logs.log_info('reg=%x got %08x was %08x' %
(Reg, Val, self.regs[Reg]))
self.regs[Reg] = Val
def initial(Id):
Id = logs.intx(Id)
PP = veri.peek_mem('tb.paths', str(Id))
Path = logs.bin2str(PP)
print 'my id', Id, Path
Workers
def peek(Sig):
Full = '%s.%s' % (Base, Sig)
if Full not in Values:
logs.log_error('sig %s not in path %s' % (Sig, Base))
return -1
return logs.intx(Values[Full][0])
def peek(Sig):
return logs.intx(peekbin(Sig))
