def elaborate(self, platform):
m = Module()
if WITH_ILA:
m.submodules.ila = self.ila
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
# Create our core SuperSpeed device.
m.submodules.usb = USBSuperSpeedDevice(phy=phy)
if WITH_ILA:
m.d.comb += [
# ILA
self.serdes_rx.eq(phy.source.data),
self.ctrl.eq(phy.source.ctrl),
self.valid.eq(phy.source.valid),
self.ila.trigger.eq(phy.source.data.word_select(3, 8) == 0xbc)
]
# Return our elaborated module.
return m
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
# Create our core SuperSpeed device.
m.submodules.usb = usb = USBSuperSpeedDevice(phy=phy)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Create our example bulk endpoint.
stream_in_ep = SuperSpeedStreamInEndpoint(
endpoint_number=self.BULK_ENDPOINT_NUMBER,
max_packet_size=self.MAX_BULK_PACKET_SIZE
)
usb.add_endpoint(stream_in_ep)
# Create a simple, monotonically-increasing data stream, and connect that up to
# to our streaming endpoint.
counter = Signal(16)
stream_in = stream_in_ep.stream
# Always provide our counter as the input to our stream; it will be consumed
# whenever our stream endpoint can accept it.
m.d.comb += [
stream_in.data .eq(counter),
stream_in.valid .eq(0b1111)
]
# Increment our counter whenever our endpoint is accepting data.
with m.If(stream_in.ready):
m.d.ss += counter.eq(counter + 1)
# Return our elaborated module.
return m
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
# Create our core SuperSpeed device.
m.submodules.usb = usb = USBSuperSpeedDevice(phy=phy)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Return our elaborated module.
return m
def elaborate(self, platform):
m = Module()
if WITH_ILA:
m.submodules.ila = self.ila
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
# Create our core SuperSpeed device.
m.submodules.usb = usb = USBSuperSpeedDevice(phy=phy, sync_frequency=50e6)
# Heartbeat LED.
counter = Signal(28)
m.d.ss += counter.eq(counter + 1)
m.d.comb += [
platform.get_led(m, 0).o.eq(usb.link_trained),
# Heartbeat.
platform.get_led(m, 7).o.eq(counter[-1])
]
if WITH_ILA:
m.d.comb += [
# ILA
self.ila_data .eq(usb.rx_data_tap.data),
self.ila_ctrl .eq(usb.rx_data_tap.ctrl),
self.ila_valid .eq(usb.rx_data_tap.valid),
self.ila.trigger .eq(usb.link_trained)
]
# Return our elaborated module.
return m